Solder bump structures for semiconductor device packaging is provided. In one embodiment, a solder bump structure comprises a semiconductor substrate, the substrate has at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad. At least one patterned and etched polymer layer is formed on a portion of the contact pad. At least one patterned and etched conductive metal layer is formed above the polymer layer and is aligned therewith. And at least one layer of solder material having a solder height is provided above the conductive metal layer, the layer of solder is aligned with the conductive metal layer, the layer of solder is thereafter reflown thereby creating a solder ball.
1. A bump structure on a semiconductor substrate comprising:
a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad;
at least one patterned and etched polymer layer formed directly on a central portion of the contact pad, wherein height of the patterned and etched polymer layer is less than ½ width of the contact pad;
at least one patterned and etched conductive metal layer formed directly above the polymer layer and being aligned therewith, wherein thickness of the patterned and etched conductive metal layer exceeds ⅓ height and ⅓ width of the patterned and etched polymer layer; and
at least one layer of solder material having a solder height provided above the conductive metal layer, the layer of solder being aligned with the conductive metal layer, the layer of solder having been reflown thereby creating a solder ball.
2. The bump structure of claim 1 , wherein the contact pad is a material selected from the group consisting of copper, copper alloy, aluminum, aluminum alloy, and combinations thereof.
3. The bump structure of claim 1 , wherein the passivation layer is a material selected from the group consisting of silicon nitride (SiN), silicon dioxide (SiO 2 ) and silicon oxynitride (SiON).
4. The bump structure at claim 1 , wherein the polymer layer comprises polyimide and has a thickness of from about 5 microns to about 100 microns.
5. The bump structure of claim 1 , wherein the polymer layer comprises epoxy and has a thickness of from about 5 microns to about 100 microns.
6. The bump structure of claim 1 , wherein the conductive metal layer comprises a UBM (Under Bump Metal) layer.
7. The bump structure of claim 6 , wherein the UBM layer comprises:
an adhesion layer;
a wetting layer formed above the adhesion layer; and
a protection layer formed above the wetting layer.
8. A bump structure on a semiconductor substrate comprising:
a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad;
at least one patterned and etched polymer layer formed directly on a central portion of the contact pad, wherein height of the patterned and etched polymer layer is less than ½ width of the contact pad;
at least one patterned and etched conductive metal layer formed directly above the surfaces of the polymer layer and the contact pad and portions of the passivation layer, the conductive metal layer being aligned with the polymer layer, wherein thickness of the patterned and etched conductive metal layer exceeds ⅓ height and ⅓ width of the patterned and etched polymer layer; and
at least one layer of solder material having a solder height provided above the conductive metal layer, the layer of solder being aligned with the conductive metal layer, the layer of solder having been reflown thereby creating a solder ball.
9. The bump structure of claim 8 , wherein the polymer layer comprises polyimide and has a thickness of from about 5 microns to about 100 microns.
10. The bump structure of claim 8 , wherein the polymer layer comprises epoxy and has a thickness of from about 5 microns to about 100 microns.
11. The bump structure of claim 8 , wherein the conductive metal layer comprises a UBM (Under Bump Metal) layer.
12. The bump structure of claim 11 , wherein the UBM layer comprises:
an adhesion layer;
a wetting layer formed above the adhesion layer; and
a protection layer formed above the wetting layer.
13. A bump structure on a semiconductor substrate comprising:
a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad;
at least one patterned and etched polymer layer formed directly on the exposed surface of the contact pad, wherein height of the patterned and etched polymer layer is less than ½ width of the contact pad;
at least one patterned and etched conductive metal layer formed directly above the surfaces of the polymer layer and portions of the passivation layer, the conductive metal layer being aligned with the polymer layer, wherein thickness of the patterned and etched conductive metal layer exceeds ⅓ height and ⅓ width of the patterned and etched polymer layer; and
at least one layer of solder material having a solder height provided above the conductive metal layer, the layer of solder being aligned with the conductive metal layer, the layer of solder having been reflown thereby creating a solder ball.
14. The bump structure of claim 13 , wherein the polymer layer comprises polyimide and has a thickness of from about 5 microns to about 100 microns.
15. The bump structure of claim 13 , wherein the polymer layer comprises epoxy and has a thickness of from about 5 microns to about 100 microns.
16. The bump structure of claim 13 , wherein the conductive metal layer ( 16 ) comprises a UBM (Under Bump Metal) layer.
17. The bump structure of claim 16 , wherein the UBM layer comprises:
an adhesion layer;
a wetting layer formed above the adhesion layer; and
a protection layer formed above the wetting layer.
18. A bump structure on a semiconductor device comprising:
a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad;
at least one patterned and etched polymer layer formed directly on a central portion of the contact pad, wherein height of the patterned and etched polymer layer is less than ½ width of the contact pad;
at least one patterned and etched conductive metal layer formed directly above the polymer layer and being aligned therewith, wherein thickness of the patterned and etched conductive metal layer exceeds ⅓ height and ⅓ width of the patterned and etched polymer layer; and
at least one layer of solder material having a solder height provided above the conductive metal layer, the layer of solder being aligned with the conductive metal layer, the layer of solder having been reflown thereby creating a solder ball.
19. A bump structure on a semiconductor wafer comprising:
a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad;
at least one patterned and etched polymer layer formed directly on a central portion of the contact pad, wherein height of the patterned and etched polymer layer is less than ½ width of the contact pad;
at least one patterned and etched conductive metal layer formed directly above the polymer layer and being aligned therewith, wherein thickness of the patterned and etched conductive metal layer exceeds ⅓ height and ⅓ width of the patterned and etched polymer layer; and
at least one layer of solder material having a solder height provided above the conductive metal layer, the layer of solder being aligned with the conductive metal layer, the layer of solder having been reflown thereby creating a solder ball.
20. A flip chip substrate comprising:
a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad;
at least one patterned and etched polymer layer formed directly on a central portion of the contact pad, wherein height of the patterned and etched polymer layer is less than ½ width of the contact pad;
at least one patterned and etched conductive metal layer formed directly above the polymer layer and being aligned therewith, wherein thickness of the patterned and etched conductive metal layer exceeds ⅓ height and ⅓ width of the patterned and etched polymer layer; and
at least one layer of solder material having a solder height provided above the conductive metal layer, the layer of solder being aligned with the conductive metal layer, the layer of solder having been reflown thereby creating a solder ball.
21. A flip chip package structure comprising:
a semiconductor substrate having at least one contact pad and an upper passivation layer having at least one opening formed therein exposing a portion of the contact pad;
at least one patterned and etched polymer layer directly formed directly on a central portion of the contact pad, wherein height of the patterned and etched polymer layer is less than ½ width of the contact pad;
at least one patterned and etched conductive metal layer formed directly above the polymer layer and being aligned therewith, wherein thickness of the patterned and etched conductive metal layer exceeds ⅓ height and ⅓ width of the patterned and etched polymer layer; and
at least one layer of solder material having a solder height provided above the conductive metal layer, the layer of solder being aligned with the conductive metal layer, the layer of solder having been reflown thereby creating a solder ball.