Semiconductor package with stacked chips and method for fabricating the same
View Patent ↗A semiconductor package with stacked chips and a method for fabricating the same are proposed. The semiconductor package includes a lead frame having a plurality of leads and supporting extensions; at least one preformed package having an active surface, and a non-active surface attached to the supporting extensions of the lead frame; at least one chip mounted on the active surface of the preformed package; a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the chip; and an encapsulant for encapsulating the preformed package, the chip, the bonding wire and a portion of the lead frame. The active surface of the preformed package serves for carrying the chip and can be used as a wire jumper, so as to solve a known good die (KGD) problem of a multi-chip module.
1. A semiconductor package with stacked chips, comprising:
a lead frame having a plurality of leads and supporting extensions;
at least one preformed package having an active surface and a non-active surface, the non-active surface being attached to the plurality of supporting extensions of the lead frame, wherein the preformed package further comprises at least a first chip and a substrate;
at least a second chip mounted on the active surface of the preformed package, wherein the active surface of the preformed package is a surface of the substrate free of being mounted with the first chip;
a plurality of bonding wires for electrically interconnecting the lead frame, the preformed package and the second chip; and
an encapsulant formed on the lead frame, for encapsulating the preformed package, the second chip, the bonding wires and a portion of the lead frame.
2. The semiconductor package of claim 1 , wherein the first chip is mounted on a surface of the substrate opposite to the active surface.
3. The semiconductor package of claim 2 , wherein the preformed package is a land grid array (LGA) package.
4. The semiconductor package claim 1 , wherein the substrate is a printed circuit board.
5. The semiconductor package of claim 4 , wherein the printed circuit board is a build-up substrate.
6. The semiconductor package of claim 4 , wherein the printed circuit board is a laminated substrate.
7. The semiconductor package of claim 1 , wherein the substrate comprises a plurality of fingers.
8. The semiconductor package of claim 1 , wherein a surface of the second chip free of being attached to the active surface of the preformed package is formed with a plurality of bond pads.