IP Library Granted Patent US 7,212,573
Granted Patent B2
US 7,212,573 · App. 10/461,780 · Granted May 1, 2007

Method and/or apparatus for determining minimum positive reference indices for a direct prediction mode

Assignee: LSI Logic Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,212,573
App. No.
10/461,780
Granted
May 1, 2007
Kind
B2
Abstract

An apparatus comprising a first processing circuit and a second processing circuit. The first processing circuit may be configured to generate (i) one or more prediction samples and (ii) a plurality of macroblocks, in response to each frame of an input video signal. The second processing circuit may be configured to (i) select one or more reference indices for each of the macroblocks from one or more sets of reference indices and (ii) generate said one or more prediction samples in response to said selected reference indices. Each of the selected reference indices is generally determined based upon minimum and maximum values for each of the one or more sets of reference indices.

Claims (28)

1. An apparatus comprising:

a first processing circuit configured to generate (i) one or more prediction samples and (ii) a plurality of macroblocks in response to each frame of an input video signal;

a second processing circuit configured (i) to select one or more reference indices for each of said macroblocks from one or more sets of reference indices and (ii) to generate said one or more prediction samples in response to said selected reference indices, wherein each of said selected reference indices is determined based upon minimum and maximum values for each of said one or more sets of reference indices.

2. The apparatus according to claim 1 , wherein said first circuit is further configured to generate transformed and quantized data in response to said plurality of macroblocks and said one or more prediction samples.

3. The apparatus according to claim 2 , further comprising:

an encoding circuit configured to generate an encoded bitstream in response to said transformed and quantized data.

4. The apparatus according to claim 1 , wherein each of said macroblocks is segmented into one or more sub-macroblocks.

5. The apparatus according to claim 1 , wherein said reference indices are selected using an operand equation that presents the maximum of a first and a second input when both inputs are negative.

6. The apparatus according to claim 1 , wherein said operand equation processes one of said macroblocks on each cycle of a clock.

7. The apparatus according to claim 6 , wherein said macroblocks comprise B-frame macroblocks.

8. The apparatus according to claim 1 , wherein said processing circuit comprises a first mode configured to process temporal direct luma references.

9. The apparatus according to claim 8 , wherein said first mode comprises an inter prediction mode.

10. A method for processing a digital video signal comprising the steps of:

(A) generating a plurality of macroblocks for each frame of said digital video signal;

(B) calculating a set of one or more reference indices for each of said macroblocks, wherein each of said one or more reference indices is calculated using an operand equation configured to present a minimum value of a first input and second input when both of said first and second inputs are positive and a maximum value of said first and second input when either or both of said first input and said second input are not positive; and

(C) generating one or more prediction samples for a current macroblock in response to said set of indices for said current macroblock.

11. The method according to claim 10 , wherein said method is further configured to generate transformed and quantized data in response to said plurality of macroblocks and said one or more prediction samples.

12. The method according to claim 11 , further comprising the step of:

generating an encoded bitstream in response to said transformed and quantized data.

13. The method according to claim 11 , wherein each of said macroblocks is segmented into one or more sub-macroblocks.

14. The method according to claim 11 , wherein said reference indices are selected using an operand equation that presents the maximum of a first and a second input when both inputs are negative.

15. The method according to claim 11 , wherein said operand equation processes one of said macroblocks on each cycle of a clock.

16. An apparatus comprising:

a first processing circuit configured to decode a bitstream in response to (i) one or more prediction samples and (ii) a plurality of macroblocks in response to each frame of an input video signal;

a second processing circuit configured (i) to select one or more reference indices for each of said macroblocks from one or more sets of reference indices and (ii) to generate said one or more prediction samples in response to said selected reference indices, wherein each of said selected reference indices is determined based upon minimum and maximum values for each of said one or more sets of reference indices.

17. The apparatus according to claim 16 , further comprising:

a generator circuit configured to generate said one or more sets of reference indices in response to (i) a macroblock partition parameter and (ii) a submacroblock partition parameter; and

a control circuit configured to generate said macroblock partition parameter in response to said plurality of macroblocks and one or more control signals.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Continuity (1)
Related Publication 20040252760A1 · Dec 16, 2004