Pseudo-random binary sequence checker with automatic synchronization
View Patent ↗A pseudo-random binary sequence checker having automatic synchronization is disclosed. The pseudo-random binary sequence checker includes a receiver, a synchronizer, and a comparator. The receiver is capable of receiving a pseudo-random binary sequence, which is generated by a pseudo-random binary sequence generator, in a parallel fashion n bits at a time. The synchronizer automatically synchronizes the state of the receiver with an n-bit sample within the pseudo-random binary sequence and calculate all subsequent n-bit sample within the pseudo-random binary sequence. The comparator compares the subsequent calculated n-bit sample within the pseudo-random binary sequence to the next subsequent next received n-bit sample within the pseudo-random binary sequence to indicate an error condition has occurred if each calculated n-bit sample within the pseudo-random binary sequence does not equal to the corresponding received n-bit sample within the pseudo-random binary sequence.
1. A parallel pseudo-random binary sequence checker comprising:
a receiving means for receiving a pseudo-random binary sequence, wherein said pseudo-random binary sequence is generated by a pseudo-random binary sequence generator n bits at a time in parallel;
means for automatically synchronizing the state of said receiving means with an n-bit sample within said pseudo-random binary sequence to generate a next n-bit sample within said pseudo-random binary sequence;
means for comparing said next generated n-bit sample within said pseudo-random binary sequence to a corresponding next received n-bit sample within said pseudo-random binary sequence; and
means for indicating an error condition has occurred if said next generated n-bit sample within said pseudo-random binary sequence does not equal to said corresponding next received n-bit sample within said pseudo-random binary sequence.
2. The checker of claim 1 , wherein said checker further includes
means for loading 16 most significant bits to said checker;
means for loading 15 least significant bits to said checker; and
means for serially advancing a plurality of latches within said checker twice.
3. The checker of claim 1 , wherein said checker further includes a multiplexor within said pseudo-random binary sequence generator for yielding output bits in parallel.
4. The checker of claim 1 , wherein said checker further includes a mask register for masking specific bits in error.
5. The checker of claim 1 , wherein said checker further includes an error counter for counting a number of errors occurred since said checker was reset.
6. The checker of claim 1 , wherein said checker further includes a sync detector to indicate an occurrence of a failed synchronization.
7. A method for synchronizing a parallel pseudo-random binary sequence checker, said method comprising:
receiving a pseudo-random binary sequence by a receiving means, wherein said pseudo-random binary sequence is generated by a pseudo-random binary sequence generator n bits at a time in parallel;
automatically synchronizing the state of said receiving means with an n-bit sample within said pseudo-random binary sequence to generate a next n-bit sample within said pseudo-random binary sequence;
comparing said next generated n-bit sample within said pseudo-random binary sequence to a corresponding next received n-bit sample within said pseudo-random binary sequence; and
indicating an error condition has occurred if said next generated n-bit sample within said pseudo-random binary sequence does not equal to said corresponding next received n-bit sample within said pseudo-random binary sequence.
8. The method of claim 7 , wherein said method further includes
loading 16 most significant bits to said parallel pseudo-random binary sequence checker;
loading 15 least significant bits to said parallel pseudo-random binary sequence checker; and
serially advancing a plurality of latches within said parallel pseudo-random binary sequence checker twice.
9. The method of claim 7 , wherein said method further includes providing a multiplexor within said pseudo-random binary sequence generator for yielding output bits in parallel.
10. The method of claim 7 , wherein said method further includes providing a mask register for masking specific bits in error.
11. The method of claim 7 , wherein said method further includes providing an error counter to count a number of errors occurred since said parallel pseudo-random binary sequence checker was previously reset.
12. The method of claim 7 , wherein said method further includes providing a logical indication of an occurrent of a failed synchronization.