Low voltage CMOS differential amplifier
A low voltage CMOS differential amplifier is provided. More specifically, there is provided a device comprising a differential pair coupled to a first tail current transistor and to a component wherein the first tail current transistor is configured to provide a tail current to the differential pair and the component is configured to provide a tail current to the differential pair when the first tail current transistor is operating in a triode region or in a cut-off region.
1. A device comprising:
a differential pair;
a first transistor, being coupled to the differential pair, and configured to provide a current to the differential pair, wherein the first transistor is self-biased;
a component, being coupled to the differential pair, and configured to provide the current to the differential pair when the first transistor is operating in a triode region or in a cut-off region; and
wherein the component is component is configured to provide over 90% of the current to the differential pair when a supply voltage to the first transistor is less than 1.2 volts.
2. The device, as set forth in claim 1 , comprising a current mirror coupled to the differential pair.
3. The device, as set forth in claim 1 , wherein the differential pair comprises a pair of NMOS transistors.
4. The device, as set forth in claim 1 , wherein the component comprises a resistor.
5. The device, as set forth in claim 1 , wherein the component comprises a second transistor.
6. The device, as set forth in claim 5 , wherein the second transistor comprises a fixed-biased transistor.
7. The device, as set forth in claim 6 , comprising a voltage source coupled to the second transistor, wherein the voltage source coupled to the second transistor comprises a voltage source coupled to a gate terminal of the second transistor.
8. The device, as set forth in claim 6 , comprising a voltage source coupled to the second transistor, wherein the voltage source coupled to the second transistor comprises the voltage source coupled to a source terminal of the second transistor.
9. A device comprising a differential amplifier, wherein the differential amplifier comprises a fixed biased transistor coupled in parallel to a self-biased transistor and wherein the fixed biased transistor and the self-biased transistor are configured to provide a current to the differential amplifier and wherein the fixed biased transistor is configured to provide over 90% of the current to the differential pair when a supply voltage to the self-biased transistor is less than 1.3 volts.
10. The device, as set forth in claim 9 , wherein a gate terminal of the fixed biased transistor is coupled to a supply voltage.
11. The device, as set forth in claim 9 , wherein a gate terminal of the fixed biased transistor is coupled to ground.
12. The device, as set forth in claim 9 , wherein the device comprises an input buffer.
13. The device, as set forth in claim 9 , wherein the device comprises a memory device.
14. The device, as set forth in claim 9 , wherein the device comprises a processor.
15. A method of operating a device comprising:
providing a supply voltage to a differential amplifier;
biasing a fixed biased transistor disposed on the differential amplifier;
biasing a self-biased transistor coupled in parallel to the fixed biased transistor; and
providing a current to a differential pair within the differential amplifier, wherein the current is at least partially provided by the fixed biased transistor and wherein the fixed biased transistor is configured to provide over 90% of the current to the differential pair when a supply voltage to the self-biased transistor is less than 1.3 volts.
16. The method, as set forth in claim 15 , wherein providing the current to the differential pair within the differential amplifier comprises providing the current, wherein the current is at least partially provided by the self-biased transistor.
17. A system comprising:
a processor; and
a memory device operatively coupled to the processor, the memory device comprising:
a differential pair;
a first transistor, being coupled to the differential pair, and configured to provide a current to the differential pair, wherein the first transistor is self-biased;
a second transistor, being coupled to the differential pair, and configured to provide the current to the differential pair when the first transistor is operating in a triode region; and
wherein the second transistor is configured to provide over 90% of the current to the differential pair when a supply voltage to the first transistor is less than 1.3 volts.
18. A device comprising:
a differential pair including a first transistor and a second transistor;
a third transistor coupled to the first transistor and the second transistor and configured to provide a supply current to the first transistor and the second transistor, wherein the third transistor is self-biased;
a component, being coupled to the first transistor and the second transistor and configured to provide the supply current to the first transistor and the second transistor when the third transistor is operating in a triode region or in a cut-off region; and
wherein the second transistor is configured to provide over 90% of the current to the differential pair when a supply voltage to the third transistor is less than 1.3 volts.
19. The device, as set forth in claim 18 , wherein the component comprises a resistor.
20. The device, as set forth in claim 18 , wherein the component comprises a fixed-biased transistor.
21. The device, as set forth in claim 18 , wherein a first input is coupled to a gate terminal of the first transistor and wherein a second input is coupled to a gate terminal of the second transistor.