IP Library Granted Patent US 7,235,849
Granted Patent B2
US 7,235,849 · App. 10/781,811 · Granted Jun 26, 2007

Semiconductor device and method for fabricating the same

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,235,849
App. No.
10/781,811
Granted
Jun 26, 2007
Kind
B2
Abstract

The semiconductor device comprises a silicon substrate 10 having a device region 11 , a transistor including a gate electrode 20 formed in the device region 11 with the gate insulation film 14 formed therebetween, and a dummy metal layer 52 formed over the gate electrode 20 with an inter-layer insulation film 32 formed therebetween, formed of a metal material having the property of occluding hydrogen and having a peripheral part positioned outer of a region where the region for the gate electrode 20 formed in and the device region 11 overlap each other.

Claims (18)

1. A semiconductor device comprising:

a semiconductor substrate having a first device region and a second device region;

a first transistor including a first gate electrode formed in the first device region with a first gate insulation film formed therebetween;

a second transistor forming a pair with the first transistor and including a second gate electrode formed in the second device region with a second gate insulation film formed therebetween;

a first metal layer formed over the first gate electrode with an insulation film formed therebetween, formed of a metal material having the property of occluding hydrogen and having a peripheral part positioned outer of a region where the first gate electrode and the first device region overlap each other; and

a second metal layer formed over the second gate electrode with the insulation film formed therebetween, formed of a metal material having the property of occluding hydrogen and having a peripheral part positioned outer of a region where the second gate electrode and the second device region overlap each other,

hydrogen termination of interfaces between the semiconductor substrate and the first and second gate insulation films by hydrogen annealing being suppressed, and

the first metal layer and the second metal layer being electrically connected to each other.

2. A semiconductor device according to claim 1 , wherein the potential of the first metal layer or the second metal layer is fixed to a prescribed potential.

3. A semiconductor device according to claim 1 , wherein the potential of the first metal layer or the second metal layer is floating.

4. A semiconductor device according to claim 1 , wherein the ratio of a gap measured vertically between the semiconductor substrate and the first metal layer to a gap measured horizontally between an edge of the region where the first gate electrode and the first device region overlap each other and the peripheral part of the metal layer is 0.32 or less than 0.32.

5. A semiconductor device according to claim 1 , wherein

the first metal layer or the second metal layer is formed of a layer film of a metal film formed of the metal material having the property of occluding hydrogen, and

another metal film of a metal material which does not have the property of occluding hydrogen.

6. A semiconductor device according to claim 1 , further comprising an interconnection layer formed on the insulation film and formed of the same metal film forming the first metal layer or the second metal layer.

7. A semiconductor device according to claim 1 , wherein the metal material is titanium, magnesium, an alloy containing titanium or an alloy containing magnesium.

8. A semiconductor device according to claim 1 , wherein the first transistor or the second transistor forms a part of a differential circuit or a part of current mirror circuit.

9. A semiconductor device according to claim 4 , wherein the ratio of a gap measured vertically between the semiconductor substrate and the second metal layer to a gap measured horizontally between an edge of the region where the second gate electrode and the second device region overlap each other and the peripheral part of the second metal layer is 0.32 or less than 0.32.

Assignments (7)
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
CORRECTIVE DOCUEMNT PREVIOUSLY RECORDED ON REEL 015010 FRAME 0369 Recorded Apr 14, 2005
From: TAKAMI, MASATOSHI
To: FUJITSU LIMITED
Reel/Frame 016070/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2004
From: TAKAMI, MASATOSHI
To: FUJITSU LIMITED
Reel/Frame 015010/0369 →
Priority Claims (1)
JP 2003-327946 · Sep 19, 2003 · national
Continuity (1)
Related Publication 20050062081A1 · Mar 24, 2005