Linear half-rate phase detector for clock recovery and method therefor
There is a clock recovery circuit to correct the timing relationship between a data signal and clock signal. The clock recovery circuit comprises a phase detector having an input for receiving a clock signal having a period, an input for receiving a data signal, and an input for receiving a window signal. The window signal has a period equal to the period of the clock signal and phase difference of −90° with respect to the clock signal. The phase detector generates an up output and a down output while maintaining a phase relationship of the up output and the down output in response to the phase relationship between the clock signal and the data signal.
1. A clock recovery circuit to correct the timing relationship between a data signal and a clock signal, comprising a phase detector having:
a clock signal input having a delay block coupled thereon providing a clock_delay output, the clock-delay output coupled in a first input of a first AND gate having a second input and an output, the output of the first AND gate defining an up output, the up output being coupled to a first input of a third AND gate, the third AND gate having a second input and an output;
a window signal input;
a data signal input having a delay block coupled thereon providing a data-delay output, data-delay output coupled to a first input of a second AND gate having a second input and an output, the output of the second AND gate defining a down output, the down output being coupled to a second input of a—the third AND gate; and
a flip-flop having a data input, a clock input, a reset input, and a data output, the flip-flop data input coupled to the window signal input, the flip-flop clock input coupled to the data signal input; the data output of the flip-flop defining a data_trans output, the data_trans output being coupled to the second input of the first AND gate and coupled to the second input of the second AND gate, the reset input of the flip-flop being coupled to the output of the third AND gate.