Remote integrated circuit testing method and apparatus
View Patent ↗A method and system for remotely testing an integrated circuit installed in an integrated circuit system is presented. The integrated circuit is equipped with test structures for testing functional blocks within the integrated circuit, and a test access mechanism configured to receive test vectors for controlling the test structures. Test vectors are applied, via the parallel port of a remote computer and parallel cable, to pins of the parallel port of the integrated circuit system, which are connected to the signal ports of the test access mechanism implemented in the integrated circuit of interest, thereby allowing remote testing of the integrated circuit while the integrated circuit is installed in its native system.
1. A method for remotely controlling an integrated circuit installed in a remote system, the integrated circuit comprising one or more functional blocks, one or more test structures configured to test said one or more functional blocks, and a test access mechanism which processes test access mechanism input vectors received on corresponding respective signal ports of the test access mechanism to control the one or more test structures, the method comprising the steps of:
obtaining, via a computer, a first set of test access mechanism signal vectors each comprising a set of respective data and/or control values to be applied to the corresponding respective signal ports of the test access mechanism of the integrated circuit installed in the remote system;
transmitting, via a first communications interface in the computer, the first set of test access mechanism signal vectors to a second communications interface in the remote system, the second communications interface operating to effect application of the first set of test access mechanism signal vectors to the corresponding respective signal ports of the test access mechanism of the integrated circuit; and
receiving, via the first communications interface in the computer, a second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit and transmitted to the first communications interface of the computer by the second communications interface of the remote system.
2. The method of claim 1 , wherein:
the first set of test access mechanism signal vectors comprises a functional test suite that tests functionality of the one or more functional blocks of the integrated circuit.
3. The method of claim 1 , wherein:
the transmitting step comprises:
writing, via the computer, the first set of test access mechanism signal vectors to a first set of respective pins of a first parallel port of the computer, the first set of respective pins of the first parallel port connected via a parallel cable to a corresponding second set of respective pins of a second parallel port, the second set of respective pins of the second parallel port connected to the corresponding respective signal ports of the test access mechanism of the integrated circuit; and
the receiving step comprises:
reading the second set of test access mechanism signal vectors from the first set of respective pins of the first parallel port of the computer, the second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit.
4. The method of claim 1 , wherein the obtaining step comprises:
presenting a graphical user interface to a user, the graphical user interface providing means to input the first set of test access mechanism signal vectors; and
receiving the first set of test access mechanism signal vectors input by the user.
5. The method of claim 4 , wherein:
the first set of test access mechanism signal vectors comprises a functional test suite that tests functionality of the one or more functional blocks of the integrated circuit.
6. A computer readable storage medium tangibly embodying program instructions implementing a method for remotely controlling an integrated circuit installed in a remote system, the integrated circuit comprising one or more functional blocks, one or more test structures configured to test said one or more functional blocks, and a test access mechanism which processes test access mechanism input vectors received on corresponding respective signal ports of the test access mechanism to control the one or more test structures, the method comprising the steps of:
obtaining, via a computer, a first set of test access mechanism signal vectors each comprising a set of respective data and/or control values to be applied to the corresponding respective signal ports of the test access mechanism of the integrated circuit installed in the remote system;
transmitting, via a first communications interface in the computer, the first set of test access mechanism signal vectors to a second communications interface in the remote system, the second communications interface operating to effect application of the first set of test access mechanism signal vectors to the corresponding respective signal ports of the test access mechanism of the integrated circuit; and
receiving, via the first communications interface in the computer, a second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit and transmitted to the first communications interface of the computer by the second communications interface of the remote system.
7. The computer readable storage medium of claim 6 , wherein:
the first set of test access mechanism signal vectors comprises a functional test suite that tests functionality of the one or more functional blocks of the integrated circuit.
8. The computer readable storage medium of claim 6 , wherein:
the transmitting step comprises:
writing, via the computer, the first set of test access mechanism signal vectors to a first set of respective pins of a first parallel port of the computer, the first set of respective pins of the first parallel port connected via a parallel cable to a corresponding second set of respective pins of a second parallel port, the second set of respective pins of the second parallel port connected to the corresponding respective signal ports of the test access mechanism of the integrated circuit; and
the receiving step comprises:
reading the second set of test access mechanism signal vectors from the first set of respective pins of the first parallel port of the computer, the second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit.
9. The computer readable storage medium of claim 6 , wherein the obtaining step comprises:
presenting a graphical user interface to a user, the graphical user interface providing means to input the first set of test access mechanism signal vectors; and
receiving the first set of test access mechanism signal vectors input by the user.
10. The computer readable storage medium of claim 9 , wherein:
the first set of test access mechanism signal vectors comprises a functional test suite that tests functionality of the one or more functional blocks of the integrated circuit.
11. An apparatus for remotely controlling an integrated circuit installed in a remote system, the integrated circuit comprising one or more functional blocks, one or more test structures configured to test said one or more functional blocks, and a test access mechanism which processes test access mechanism input vectors received on corresponding respective signal ports of the test access mechanism to control the one or more test structures, the apparatus comprising:
a first communications interface operable to communicate with a second communications interface installed in the remote system, the second communications interface operable to apply test access mechanism input vectors received from said first communications interface to the corresponding respective signal ports of the test access mechanism of the integrated circuit;
a memory;
a program stored in the memory, the program comprising program instructions for performing a method comprising the steps of:
obtaining a first set of test access mechanism signal vectors each comprising a set of respective data and/or control values to be applied to the corresponding respective test access mechanism signal ports of the test access mechanism of the integrated circuit installed in the remote system;
transmitting, via the first communications interface in the computer, the first set of test access mechanism signal vectors to the second communications interface in the remote system; and
receiving, via the first communications interface in the computer, a second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit and transmitted to the first communications interface of the computer by the second communications interface of the remote system; and
a processor which executes the program stored in the memory.
12. The apparatus of claim 11 , wherein:
the first set of test access mechanism signal vectors comprises a functional test suite that tests functionality of the one or more functional blocks of the integrated circuit.
13. The apparatus of claim 11 , wherein:
the transmitting step comprises:
writing, via the computer, the first set of test access mechanism signal vectors to a first set of respective pins of a first parallel port of the computer, the first set of respective pins of the first parallel port connected via a parallel cable to a corresponding second set of respective pins of a second parallel port, the second set of respective pins of the second parallel port connected to the corresponding respective signal ports of the test access mechanism of the integrated circuit; and
the receiving step comprises:
reading the second set of test access mechanism signal vectors from the first set of respective pins of the first parallel port of the computer, the second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit.
14. The apparatus of claim 11 , wherein the obtaining step comprises:
presenting a graphical user interface to a user, the graphical user interface providing means to input the first set of test access mechanism signal vectors; and
receiving the first set of test access mechanism signal vectors input by the user.
15. The apparatus of claim 14 , wherein:
the first set of test access mechanism signal vectors comprises a functional test suite that tests functionality of the one or more functional blocks of the integrated circuit.
16. A method for remotely controlling an integrated circuit installed in a remote system, the integrated circuit comprising one or more functional blocks, one or more test structures configured to test said one or more functional blocks, and a test access mechanism which processes test access mechanism input vectors received on corresponding respective signal ports of the test access mechanism to control the one or more test structures, the method comprising the steps of:
obtaining, via a computer, a first set of test access mechanism signal vectors each comprising a set of respective data and/or control values to be applied to the corresponding respective signal ports of the test access mechanism of the integrated circuit installed in the remote system;
writing, via the computer, the first set of test access mechanism signal vectors to a first set of respective pins of a first parallel port of the computer, the first set of respective pins of the first parallel port connected via a parallel cable to a corresponding second set of respective pins of a second parallel port, the second set of respective pins of the second parallel port connected to the corresponding respective signal ports of the test access mechanism of the integrated circuit; and
reading a second set of test access mechanism signal vectors from the first set of respective pins of the first parallel port of the computer, the second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit.
17. The method of claim 16 , wherein:
the first set of test access mechanism signal vectors comprises a functional test suite that tests functionality of the one or more functional blocks of the integrated circuit.
18. A computer readable storage medium tangibly embodying program instructions implementing a method for remotely controlling an integrated circuit installed in a remote system, the integrated circuit comprising one or more functional blocks, one or more test structures configured to test said one or more functional blocks, and a test access mechanism which processes test access mechanism input vectors received on corresponding respective signal ports of the test access mechanism to control the one or more test structures, the method comprising the steps of:
obtaining, via a computer, a first set of test access mechanism signal vectors each comprising a set of respective data and/or control values to be applied to the corresponding respective signal ports of the test access mechanism of the integrated circuit installed in the remote system;
writing, via the computer, the first set of test access mechanism signal vectors to a first set of respective pins of a first parallel port of the computer, the first set of respective pins of the first parallel port connected via a parallel cable to a corresponding second set of respective pins of a second parallel port, the second set of respective pins of the second parallel port connected to the corresponding respective signal ports of the test access mechanism of the integrated circuit; and
reading a second set of test access mechanism signal vectors from the first set of respective pins of the first parallel port of the computer, the second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit.
19. The computer readable storage medium of claim 18 , wherein:
the first set of test access mechanism signal vectors comprises a functional test suite that tests functionality of the one or more functional blocks of the integrated circuit.
20. An apparatus for remotely controlling an integrated circuit installed in a remote system, the integrated circuit comprising one or more functional blocks, one or more test structures configured to test said one or more functional blocks, and a test access mechanism which processes test access mechanism input vectors received on corresponding respective signal ports of the test access mechanism to control the one or more test structures, the apparatus comprising:
a first parallel port comprising a first set of respective pins that are connectable via a parallel cable to a corresponding second set of respective pins of a second parallel port installed in the remote system, the second set of respective pins of the second parallel port connected to the corresponding respective signal ports of the test access mechanism of the integrated circuit;
a memory;
a program stored in the memory, the program comprising program instructions for performing a method comprising the steps of:
obtaining a first set of test access mechanism signal vectors each comprising a set of respective data and/or control values to be applied to the corresponding respective test access mechanism signal ports of the test access mechanism of the integrated circuit installed in the remote system;
writing the first set of test access mechanism signal vectors to the first set of respective pins of the first parallel port; and
reading a second set of test access mechanism signal vectors from the first set of respective pins of the first parallel port of the computer, the second set of test access mechanism signal vectors comprising test result data output onto said the corresponding respective signal ports of the test access mechanism of the integrated circuit; and
a processor which executes the program stored in the memory.