Flash memory devices with trimmed analog voltages
A flash memory device of the multi-level cell (MLC) type, in which control gate voltages in read and programming operations and a bandgap reference voltage source are trimmable from external terminals, is disclosed. In a special test mode, control gate voltages can be applied to a selected programmed memory cell so that the threshold voltage of the cell can be sensed. A digital-to-analog converter (DAC) use for programming and a second read/verify DAC apply varying analog voltages and are sequentially used to verify the programming of an associated set of memory cells in this special test mode, with the DAC input values that provide the closest result selected for use in normal operation. These DAC's are dependent on the value of a reference source that my also be trimmed.
1. A non-volatile memory device, comprising:
an array of non-volatile memory cells arranged in rows and columns;
circuitry for addressing at least one selected memory cell;
circuitry for sensing the state of the at least one selected memory cell;
circuitry for programming the at least one selected memory cell;
an analog voltage generator circuit for generating an analog voltage in the non-volatile memory device at a first selected voltage varying from a first nominal voltage level;
an external terminal, for receiving a voltage to be applied to the at least one selected memory cell in a special test mode, and for performing a control function in a normal operating mode; and
control logic for placing the device into the special test mode and into the normal operating mode, responsive to received commands.
2. The device of claim 1 , wherein the addressing circuitry comprises:
a row decoder and multiplexer, for applying a control gate voltage to a control gate of the at least one selected memory cell;
wherein the analog voltage generator is coupled to the row decoder and multiplexer, and is for generating the control gate voltage to be applied by the row decoder and multiplexer to the control gate of the at least one selected memory cell in the normal operating mode;
wherein the external terminal is coupled to the row decoder, so that the received voltage is applied as the control gate voltage to the at least one selected memory cell in the special test mode;
and wherein the control gate voltage generated by the analog voltage generator circuit corresponds to the first selected voltage.
3. The device of claim 2 , further comprising:
circuitry for setting the selected voltage of the analog voltage generator circuit responsive to a measured response of the at least one selected memory cell to the voltage received at the external terminal.
4. The device of claim 2 , wherein the sensing circuitry is for sensing the state of the at least one selected memory cell responsive to varying voltages at the external terminal in the special test mode;
and further comprising:
output terminals coupled to the sensing circuitry, for communicating the sensed state of the at least one selected memory cell responsive to varying voltages at the external terminal in the special test mode, so that the threshold voltage of the at least one selected memory cell can be derived.
5. The device of claim 2 , wherein the first nominal voltage corresponds to a first multi-level cell programming level;
and wherein the analog voltage generator is also for generating an analog voltage in the non-volatile memory device at a second selected voltage varying from a second nominal voltage corresponding to a second multi-level cell programming level.
6. The device of claim 5 , wherein the analog voltage generator circuit comprises a digital-to-analog-converter circuit, having a first digital input for receiving digital select signals indicating the first and second selected voltages, and having an analog output.
7. The device of claim 2 , wherein the analog voltage generator circuit comprises a digital-to-analog-converter circuit, having a digital input for receiving digital select signals indicating the first selected voltage, and having an analog output.
8. The device of claim 1 , wherein the addressing circuitry comprises:
a row decoder and multiplexer, for applying a control gate voltage to a control gate of the at least one selected memory cell;
wherein the programming circuitry comprises the analog voltage generator circuit, which comprises:
a programming DAC circuit for generating a programming voltage based on a reference voltage, so that the row decoder and multiplexer applies a voltage corresponding to the programming voltage as the control gate voltage of the at least one selected memory cell;
wherein the external terminal is coupled to the row decoder, so that the received voltage is applied as the control gate voltage to the at least one selected memory cell in the special test mode;
and wherein the programming voltage generated by the analog voltage generator circuit corresponds to the first selected voltage.
9. The device of claim 8 , further comprising
circuitry for setting the first selected voltage of the analog voltage generator circuit responsive to a measured response of the at least one selected memory cell to the voltage received at the external terminal.
10. The device of claim 8 , further comprising:
a bandgap voltage reference circuit, for generating a bandgap reference voltage;
wherein the analog voltage generator circuit has an input coupled to the bandgap voltage reference circuit, and generates the programming voltage corresponding to the bandgap reference voltage.
11. The device of claim 8 , wherein the first nominal voltage level corresponds to a first multi-level cell programming level;
and wherein the analog voltage generator circuit is also for generating a reference voltage in the normal operating mode, at a second selected voltage varying from a second nominal voltage corresponding to a second multi-level cell programming level.
12. The device of claim 11 , further comprising:
a bandgap voltage reference circuit, for generating a bandgap reference voltage;
wherein the analog voltage generator circuit has an input coupled to the bandgap voltage reference circuit, and generates programming voltages based on the bandgap reference voltage.
13. The device of claim 12 , wherein the analog voltage generator circuit comprises a digital-to-analog-converter circuit, having a first digital input for receiving digital select signals indicating the first and second selected voltages, and having an analog output.
14. The device of claim 8 , wherein the analog voltage generator circuit comprises a digital-to-analog-converter circuit, having a digital input for receiving digital select signals indicating the first selected voltage, and having an analog output.
15. The device of claim 1 , wherein the analog voltage generator circuit comprises a digital-to-analog-converter circuit, having a digital input for receiving digital select signals indicating the first selected voltage, and having an analog output.
16. The device of claim 15 , further comprising:
a store for storing a value of the digital select signal indicating the first selected voltage, the store having an output coupled to the digital input of the analog voltage generator circuit.
17. The device of claim 16 , wherein the store comprises at least one non-volatile memory element.