Built-in self test for memory arrays using error correction coding
A memory self-testing system, apparatus, and method are provided which allow for testing for a plurality of bit errors and passing memory arrays having an error level which is correctable using selected error correction coding. An exemplary system embodiment includes a memory array, a comparator, an integrator, and a test control circuit. The memory array is adapted to store input test data and output stored test data during a plurality of memory read and write test operations. The comparator compares the input test data and the stored test data for a plurality of bit positions, and provides a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions. The integrator receives the corresponding error signal and maintains the corresponding error signal for each bit position during the plurality of test operations. The test control circuit provides a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.
1. A self-test apparatus for a memory, the memory adapted to store input test data and output stored test data during a plurality of memory read and write test operations, the apparatus comprising:
a comparator coupled to receive the input test data and the stored test data, the comparator adapted to compare the input test data and the stored test data for a plurality of bit positions, and to provide a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions;
an integrator coupled to the comparator to receive the corresponding error signal, the integrator adapted to maintain the corresponding error signal for each bit position during the plurality of test operations; and
a test control circuit coupled to the integrator, the test control circuit adapted to provide a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.
2. The memory self-test apparatus of claim 1 , wherein the integrator comprises a plurality of latches, each latch of the plurality of latches corresponding to a bit position of the plurality of bit positions.
3. The memory self-test apparatus of claim 2 , wherein each latch has an output and an input, with the latch output being coupled to the latch input to maintain the corresponding error signal during the plurality of test operations.
4. The memory self-test apparatus of claim 1 , wherein the predetermined level of corresponding error signals is determined by an error correction capability of a selected error correction code.
5. The memory self-test apparatus of claim 1 , wherein the predetermined level of corresponding error signals is at least two corresponding error signals.
6. The memory self-test apparatus of claim 1 , wherein the test control circuit is further adapted to provide a pass signal when there is at most one corresponding error signal.
7. The memory self-test apparatus of claim 1 , further comprising:
a test data generator coupled to the comparator and coupled to the memory to provide the input test data.
8. The memory self-test apparatus of claim 7 , wherein the test data generator is adapted to generate a plurality of test patterns corresponding to the plurality of test operations, each test pattern of the plurality of test patterns adapted to detect single-bit errors.
9. The memory self-test apparatus of claim 1 , wherein the plurality of bit positions correspond to a data word having a plurality of data bits and a plurality of error correction bits.
10. The memory self-test apparatus of claim 1 , wherein the plurality of bit positions correspond to a plurality of data words, wherein each data word of the plurality of data words has a plurality of data bits and a plurality of error correction bits.
11. The memory self-test apparatus of claim 1 , wherein the plurality of bit positions correspond to a plurality of columns of the memory.
12. The memory self test apparatus of claim 1 , wherein the test control circuit is implemented using combinatorial and conditional logic gates which provide the fail signal when there are at least two corresponding error signals.
13. The memory self test apparatus of claim 12 , wherein the combinatorial and conditional logic gates are specified by a CASE statement which provides a pass signal when no corresponding error signal has occurred for all bit positions or when at most one corresponding error signal has occurred for all bit positions, and otherwise provides the fail signal.
14. The memory self-test apparatus of claim 1 , wherein the plurality of memory read and write test operations utilize a plurality of single-bit error test patterns.
15. The memory self-test apparatus of claim 1 , wherein the memory self test apparatus is integrated within a memory integrated circuit.
16. The memory self-test apparatus of claim 1 , wherein the memory self-test apparatus is integrated with an embedded memory of an integrated circuit having a plurality of additional, non-memory functions.
17. The memory self-test apparatus of claim 1 , wherein the memory self-test apparatus is embodied as a processor.
18. The memory self-test apparatus of claim 1 , wherein the fail signal is a first state of a memory pass/fail indicator, and wherein a memory pass is a second state of the memory pass/fail indicator.
19. A memory system, comprising:
a memory array adapted to store input test data and output stored test data during a plurality of memory read and write test operations;
a comparator coupled to the memory array to receive the input test data and the stored test data, the comparator adapted to compare the input test data and the stored test data for a plurality of bit positions, and to provide a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions;
an integrator coupled to the comparator to receive the corresponding error signal, the integrator adapted to maintain the corresponding error signal for each bit position during the plurality of test operations; and
a test control circuit coupled to the integrator, the test control circuit adapted to provide a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.
20. The memory system of claim 19 , wherein the integrator comprises a plurality of latches, each latch of the plurality of latches corresponding to a bit position of the plurality of bit positions, wherein each latch has an output coupled to an input of the latch to maintain the corresponding error signal during the plurality of test operations.
21. The memory system of claim 19 , wherein the predetermined level of corresponding error signals is determined by an error correction capability of a selected error correction code.
22. The memory system of claim 19 , wherein the predetermined level of corresponding error signals is at least two corresponding error signals.
23. The memory system of claim 19 , wherein the test control circuit is further adapted to provide a pass signal when there is at most one corresponding error signal, wherein the fail signal is a first state of a memory pass/fail indicator, and wherein a pass signal is a second state of the memory pass/fail indicator.
24. The memory system of claim 19 , further comprising:
a test data generator coupled to the comparator and to the memory array to provide the input test data, the test data generator adapted to generate a plurality of test patterns corresponding to the plurality of test operations, each test pattern of the plurality of test patterns adapted to detect single-bit errors.
25. The memory system of claim 19 , wherein the plurality of bit positions correspond to one or more data words, each data word having a plurality of data bits and a plurality of error correction bits.
26. The memory system of claim 19 , wherein the plurality of bit positions correspond to a plurality of columns of the memory array.
27. A method of testing a memory array, the memory array adapted to store input test data and output stored test data during a plurality of memory read and write test operations, the method comprising:
comparing the input test data and the stored test data for a plurality of bit positions;
providing a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions;
maintaining the corresponding error signal for each bit position during the plurality of test operations; and
providing a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions.
28. The method of testing a memory array of claim 27 , wherein the predetermined level of corresponding error signals is determined by an error correction capability of a selected error correction code.
29. The method of testing a memory array of claim 27 , wherein the predetermined level of corresponding error signals is at least two corresponding error signals.
30. The method of testing a memory array of claim 27 , further comprising:
providing a pass signal when there is at most one corresponding error signal.
31. The method of testing a memory array of claim 27 , further comprising:
generating a plurality of test patterns corresponding to the plurality of test operations, each test pattern of the plurality of test patterns adapted to detect single-bit errors.
32. The method of testing a memory array of claim 27 , wherein the plurality of bit positions correspond to a one or more data words of a plurality of data words, wherein each data word of the plurality of data words has a plurality of data bits and a plurality of error correction bits.
33. The method of testing a memory array of claim 27 , further comprising:
providing the fail signal as a first state of a memory pass/fail indicator; and
providing a pass signal as a second state of the memory pass/fail indicator.
34. A memory system, comprising:
a memory array adapted to store input test data and output stored test data during a plurality of memory read and write test operations;
a test data generator coupled to the memory array to provide the input test data, the test data generator adapted to generate a plurality of test patterns corresponding to the plurality of test operations, each test pattern of the plurality of test patterns adapted to detect single-bit errors;
a comparator coupled to the test data generator to receive the input test data and coupled to the memory array to receive the stored test data, the comparator adapted to compare the input test data and the stored test data for a plurality of bit positions, and to provide a corresponding error signal when the stored test data is not identical to the input test data for each bit position of the plurality of bit positions, wherein the plurality of bit positions correspond to one or more data words, each data word having a plurality of data bits and a plurality of error correction bits;
an integrator coupled to the comparator to receive the corresponding error signal, the integrator adapted to maintain the corresponding error signal for each bit position during the plurality of test operations; and
a test control circuit coupled to the integrator, the test control circuit adapted to provide a fail signal when a predetermined level of corresponding error signals have been provided for the plurality of bit positions, the predetermined level of corresponding error signals corresponding to an error correction capability of a selected error correction code.