Method of forming an interface for a semiconductor device
In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.
1. A method of establishing electrical contact between a semiconductor substrate and a semiconductor device, comprising:
providing a substrate with an overlying insulating layer;
etching a hole through the insulating layer to the substrate;
introducing doped polycrystalline silicon into the hole;
introducing at least one titanium layer within the hole over the doped polycrystalline silicon;
introducing at least one non-titanium layer over the at least one titanium layer and within the hole;
providing an oxidation barrier over the non-titanium layer and within the hole;
siliciding the titanium layer;
nitridizing the non-titanium layer by exposing the non-titanium layer to an N 2 /NH 3 ambient at a temperature of about 360° C.; and
forming the semiconductor device over the oxidation barrier.
2. The method of claim 1 , further comprising exposing the non-titanium layer to an N 2 /NH 3 ambient under a pressure of approximately 4.5 torr.
3. The method of claim 1 , wherein exposing the non-titanium layer to an N 2 /NH 3 ambient comprises exposing a tungsten layer to an N 2 /NH 3 ambient.
4. The method of claim 1 , wherein introducing doped polycrystalline silicon into the hole comprises filling the hole with doped polycrystalline silicon and subsequently removing a portion of the doped polycrystalline silicon from the hole.
5. The method of claim 4 , wherein removing a portion of the doped polycrystalline silicon comprises etching the doped polycrystalline silicon.
6. The method of claim 1 , further comprising siliciding the titanium layer prior to introducing at least one non-titanium layer over the at least one titanium layer and within the hole.
7. The method of claim 1 , wherein introducing at least one titanium layer comprises selectively depositing the titanium layer on the polycrystalline silicon through chemical vapor deposition.
8. The method of claim 1 , wherein siliciding the titanium layer comprises exposing the semiconductor substrate to TiCl 4 with a reactive gas and a carrier gas at a temperature about 400° C. in a reaction chamber under a pressure of approximately 0.2 to 2 torr while an RF voltage is applied to the reaction chamber.
9. The method of claim 1 , wherein the oxidation barrier is selected from the group consisting of rhenium, iridium, osmium, palladium, platinum, and rhodium.
10. A method of establishing electrical contact between a semiconductor substrate and a semiconductor device, comprising:
providing a substrate with an overlying insulating layer;
etching a hole through the insulating layer to the substrate;
introducing doped polycrystalline silicon into the hole;
introducing at least one titanium layer within the hole over the doped polycrystalline silicon;
introducing at least one non-titanium layer over the at least one titanium layer and within the hole;
siliciding the titanium layer by exposing the semiconductor substrate to TiCl 4 with a reactive gas and a carrier gas at a temperature about 400° C. in a reaction chamber under a pressure of approximately 0.2 to 2 torr while an RF voltage is applied to the reaction chamber;
nitridizing the non-titanium layer by exposing the non-titanium layer to an N 2 /NH 3 ambient at a temperature of about 360° C.; and
forming the semiconductor device over the non-titanium layer.
11. The method of claim 10 , further comprising exposing the non-titanium layer to an N 2 /NH 3 ambient under a pressure of approximately 4.5 torr.
12. The method of claim 10 , wherein exposing the non-titanium layer to an N 2 /NH 3 ambient comprises exposing a tungsten layer to an N 2 /NH 3 ambient.
13. The method of claim 10 , wherein introducing doped polycrystalline silicon into the hole comprises filling the hole with doped polycrystalline silicon and subsequently removing a portion of the doped polycrystalline silicon from the hole.
14. The method of claim 13 , wherein removing a portion of the doped polycrystalline silicon comprises etching the doped polycrystalline silicon.
15. The method of claim 10 , further comprising siliciding the titanium layer prior to introducing at least one non-titanium layer over the at least one titanium layer and within the hole.
16. The method of claim 10 , wherein introducing at least one titanium layer comprises selectively depositing the titanium layer on the polycrystalline silicon through chemical vapor deposition.