IP Library › Granted Patent US 7,262,428
Granted Patent B2
US 7,262,428 · App. 10/979,994 · Granted Aug 28, 2007

Strained Si/SiGe/SOI islands and processes of making same

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,262,428
App. No.
10/979,994
Granted
Aug 28, 2007
Kind
B2
Abstract

A process of making a strained silicon-on-insulator structure is disclosed. A recess is formed in a substrate to laterally isolate an active area. An undercutting etch forms a bubble recess under the active area to partially vertically isolate the active area. A thermal oxidation completes the vertical isolation by use of a minifield oxidation process. The recess is filled to form a shallow trench isolation structure. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.

Claims (12)

1. An article comprising:

a substrate;

a relaxed semiconductive silicon compound layer disposed above and grown in direct contact with the substrate;

a strained silicon layer disposed above and grown in direct contact with the relaxed semiconductive silicon compound layer;

wherein the strained silicon layer is laterally isolated by a shallow trench isolation, and wherein the strained silicon layer is vertically isolated by a thermal oxide disposed below and grown in direct contact with both the relaxed semiconductive silicon compound layer and the substrate.

2. The article according to claim 1 , wherein the relaxed semiconductive silicon compound layer includes a SiGe compound.

3. The article according to claim 1 , above the strained silicon layer, further including:

a storage device.

4. The article of claim 1 , wherein the thermal oxide comprises a mini field oxide.

5. The article of claim 1 , wherein the thermal oxide comprises a high pressure oxide.

6. The article of claim 1 , wherein the thermal oxide comprises a flattened field oxide.

7. The article of claim 1 , wherein the thermal oxide comprises facet faces at an oxide to substrate interface.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 1063417400 · Aug 5, 2003
Related Publication 20050087842A1 · Apr 28, 2005