Scalable high density non-volatile memory cells in a contactless memory array
A plurality of split gate non-volatile memory cells are formed vertically in a trench along the sidewalls. Each cell is comprised of a bistable element and an adjacent fixed gate threshold element that share a common respective control gate/access gate. The bistable element has a gate insulator stack that is comprised of either a floating gate or a charge trapping layer over a tunnel insulator. A plurality of silicon rich nitride layers are formed over the floating gate or charge trapping layer and separated by a high dielectric constant layer.
1. A method for fabricating an integrated non-volatile memory device, the method comprising:
forming a plurality of trenches in a substrate material, each pair of trenches defining a mesa and each trench having a top section and a bottom section;
forming a bistable element along and adjacent to each sidewall of the trenches, the bistable element having a control gate;
forming a fixed threshold element along and adjacent to each sidewall of the trenches and adjacent to the bistable element, the fixed threshold element having an access gate formed as a single layer with the control gate;
forming diffusion areas in the tops of the mesas and in the substrate at the bottoms of the trenches; and
forming a shared source line substantially in the middle of each trench.
2. The method of claim 1 wherein forming the bistable element further includes:
forming a tunnel insulator layer over the trench sidewall;
forming a floating gate layer over the tunnel oxide layer;
forming first silicon rich nitride layer over the floating gate layer;
forming a high dielectric constant insulator layer over the first silicon rich nitride layer;
forming a second silicon rich nitride layer over the high dielectric constant insulator layer; and
forming the control gate layer over the second silicon rich nitride layer.
3. The method of claim 2 wherein the tunnel insulator layer is an oxide layer.
4. The method of claim 1 wherein forming the bistable element further includes:
forming a tunnel insulator layer over the trench sidewall;
forming a trapping layer over the tunnel oxide layer;
forming first silicon rich nitride layer over the trapping layer;
forming a high dielectric constant insulator layer over the first silicon rich nitride layer;
forming a second silicon rich nitride layer over the high dielectric constant insulator layer; and
forming the control gate layer over the second silicon rich nitride layer.
5. The method of claim 1 wherein forming the plurality of trenches comprises forming the top section to be narrower than the bottom section.
6. The method of claim 1 wherein forming the plurality of trenches comprises forming the top section to be wider than the bottom section.
7. The method of claim 1 wherein the bistable element is formed in the top section and the fixed threshold element is formed in the bottom section.
8. A method for fabricating an integrated non-volatile memory device, the method comprising:
forming a plurality of trenches in a substrate material, each pair of trenches defining a mesa;
forming a planar bistable element on each mesa wherein each planar bistable element is comprised of a first insulator layer over each mesa, one of a trapping layer or a floating gate over the first insulator layer, a first silicon rich nitride layer over the trapping or floating gate, a second insulator layer over the first silicon rich nitride layer, a second silicon rich nitride layer over the second insulator layer, and a control gate over the second silicon rich nitride layer;
forming a fixed threshold element along each sidewall of the trenches and substantially adjacent to the bistable element;
forming a shared source line diffusion area in substrate at the bottom of each trench; and
forming a shared source line substantially in the middle of each trench.
9. The method of claim 8 wherein forming the fixed threshold element comprises forming a select gate layer substantially parallel to the sidewall.
10. The method of claim 8 wherein the trapping layer comprises a high dielectric constant material having one of metal nano-dots or silicon nano-crystals.
11. The method of claim 10 wherein the metal nano-dots comprise one of: platinum (Pt), gold (Au), Cobalt (Co), or Tungsten (W).
12. The method of claim 10 wherein the metal nano-dots have a density in the range of 5×10 12 to 10×10 13 , dot sizes in the range of 1-3 nm, and spaced greater than 3 nm.
13. A method for fabricating an integrated non-volatile memory integrated circuit, the method comprising:
forming a plurality of mesas in a p-type substrate material, each pair of mesas defining a trench and each mesa having a top section and a bottom section;
forming a bistable element at the top section along opposing sidewalls of each mesa, the bistable element having a control gate;
forming a fixed threshold element along opposing sidewalls at the bottom section and adjacent to both the bistable element and the sidewall, the fixed threshold element having an access gate that is formed as a single layer common control gate with the control gate;
doping n× diffusion areas in the top of each mesa between and substantially adjacent two bistable elements and in the substrate at the bottom of each trench; and
forming a shared source line in each trench between each pair of mesas.
14. The method of claim 13 wherein the top section is formed narrower than the bottom section.
15. The method of claim 13 wherein forming the shared source line comprises forming a pillar in each trench that is coupled to the diffusion area at the bottom of the trench.
16. The method of claim 13 and further comprising forming an oxide material on either side of the shared source line between the source line and the mesa sidewalls.
17. The method of claim 13 wherein the single layer common control gate is comprised of polysilicon.