Field effect transistor having source and/or drain forming Schottky or Schottky-like contact with strained semiconductor substrate
The present invention is a field effect transistor having a strained semiconductor substrate and Schottky-barrier source and drain electrodes, and a method for making the transistor. The bulk charge carrier transport characteristic of the Schottky barrier field effect transistor minimizes carrier surface scattering, which enables the strained substrate to provide improved power and speed performance characteristics in this device, as compared to conventional devices.
1. A device for regulating the flow of electric current, the device comprising:
a strained channel region;
a gate electrode on the strained channel region; and
a source electrode and a drain electrode in contact with the strained channel region, at least one of the source electrode and the drain electrode forming a Schottky or Schottky-like contact with the strained channel region.
2. The device of claim 1 , wherein the source electrode and the drain electrode are formed from a member of the group consisting of: Platinum Silicide, Palladium Silicide, and Iridium Silicide.
3. The device of claim 1 , wherein the source electrode and the drain electrode are formed from a member of the group consisting of the rare-earth silicides.
4. The device of claim 1 , wherein at least one of the source and drain electrodes forms a Schottky or Schottky-like contact with the strained channel region.
5. The device of claim 1 , wherein an entire interface between at least one of the source and the drain electrodes and the strained channel region forms a Schottky contact or Schottky-like contact.
6. The device of claim 1 , wherein the strained channel region has channel dopants and a channel dopant concentration.
7. The device of claim 6 , wherein the channel dopant concentration varies significantly in a vertical direction and is generally constant in a lateral direction.
8. The device of claim 7 , wherein a channel length of the strained channel region is less than or equal to about 100 nm.
9. The device of claim 6 , wherein the channel dopant concentration varies significantly in the vertical and lateral directions.
10. The device of claim 9 , wherein a channel length of the strained channel region is less than or equal to about 100 nm.
11. The device of claim 6 , wherein the channel dopants are selected from the group consisting of: Arsenic, Phosphorous, Antimony, Boron, Indium, and Gallium.
12. The device of claim 1 , wherein a channel length of the strained channel region is less than or equal to about 100 nm.
13. The device of claim 1 , wherein the gate electrode comprises:
a gate insulator including an electrically insulating layer disposed on the strained channel region; and
a conducting film on the insulating layer.
14. The device of claim 13 , wherein the gate electrode further comprises a gate sidewall spacer comprising at least one sidewall insulating layer on at least one sidewall of the gate electrode.
15. The device of claim 13 , wherein the gate insulator has a dielectric constant greater than 4.0.
16. The device of claim 13 , wherein the strained channel region has channel dopants and a channel dopant concentration.
17. The device of claim 16 , wherein the channel dopant concentration varies significantly in a vertical direction and is generally constant in a lateral direction.
18. The device of claim 16 , wherein the channel dopant concentration varies significantly in the vertical and lateral direction.
19. The device of claim 16 , wherein the strained channel region is formed on a SOI substrate.
20. The device of claim 13 , wherein the gate insulator is formed from a member of the group consisting of metal oxides.
21. The device of claim 13 , wherein the conducting film is formed from a member of the group consisting of metals.
22. The device of claim 1 , wherein the strained channel region is formed on a SOI substrate.
23. The device of claim 1 , wherein the device is a MOSFET.
24. A device for regulating the flow of electric current, the device comprising:
a semiconductor substrate;
a gate electrode on the semiconductor substrate; and
a source electrode and a drain electrode in contact with the semiconductor substrate, at least one of the source electrode and the drain electrode forming a Schottky or Schottky-like contact with the semiconductor substrate, the source and the drain separated by a strained channel region.
25. The device of claim 24 , wherein the source electrode and the drain electrode are formed from a member of the group consisting of: Platinum Silcide, Palladium Silicide, and Iridium Silicide.
26. The device of claim 24 , wherein the source electrode and the drain electrode are formed from a member of the group consisting of rare-earth suicides.
27. The device of claim 24 , wherein at least one of the source and drain electrodes forms a Schottky or Schottky-like contact with at least the strained channel region.
28. The device of claim 24 , wherein an entire interface between at least one of the source and the drain electrodes and the strained channel region forms a Schottky contact or Schottky-like contact with the strained channel region.
29. The device of claim 24 wherein the strained channel region has channel dopants and further has a channel dopant concentration.
30. The device of claim 29 , wherein the channel dopant concentration varies significantly in a vertical direction and is generally constant in a lateral direction.
31. The device of claim 30 , wherein a channel length of the strained channel region is less than or equal to about 100 nm.
32. The device of claim 29 , wherein the channel dopant concentration varies significantly in vertical and lateral directions.
33. The device of claim 32 , wherein a channel length of the strained channel region is less than or equal to about 100 nm.
34. The device of claim 29 wherein the channel dopants are selected from the group consisting of: Arsenic, Phosphorous, Antimony, Boron, Indium, and Gallium.
35. The device of claim 24 , wherein a channel length is less than or equal to about 100 nm.
36. The device of claim 24 , wherein the gate electrode comprises:
a gate insulator including an electrically insulating layer disposed on the semiconductor substrate; and
a conducting film on the insulating layer.
37. The device of claim 36 , wherein the gate electrode further comprises a gate sidewall spacer comprising at least one sidewall insulating layer on at least one sidewall of the gate electrode.
38. The device of claim 36 , wherein the gate insulator has a dielectric constant greater than 4.0.
39. The device of claim 38 , wherein the strained channel region has channel dopants and a channel dopant concentration.
40. The device of claim 39 , wherein the channel dopant concentration varies significantly in a vertical direction and is generally constant in a lateral direction.
41. The device of claim 39 , wherein the channel dopant concentration varies significantly in vertical and lateral direction.
42. The device of claim 39 wherein the semiconductor substrate is a SOI substrate.
43. The device of claim 36 , wherein the gate insulator is formed from a member of the group consisting of metal oxides.
44. The device of claim 36 , wherein the conducting film is formed from a member of the group consisting of metals.
45. The device of claim 24 , wherein the semiconductor substrate is a SOI substrate.
46. The device of claim 24 , wherein the device is a MOSFET.