Semiconductor multi-chip package and fabrication method
A multi-chip package comprises a package substrate having bond fingers disposed thereon. A first chip have center bonding pads formed on a substantially center portion thereof. The first chip is disposed on the package substrate. Insulating support structures are formed on the first chip located outward of the bonding pads. A bonding wire is connected between one of the bond fingers and at least one of the center bonding pads. A second chip has is disposed over the bonding wire and overlying the insulating support structures.
1. A multi-chip package, comprising:
a package substrate;
a first chip mounted on the package substrate, the first chip having center bonding pads on a substantially center portion thereof;
a plurality of separate, mound-like insulating support structures formed on the first chip, the plurality of insulating support structures located outward of the first bonding pads;
a second chip stacked on the first chip, the second chip electrically connected to the package substrate; and
a bonding wire electrically connected between the package substrate and the center bonding pads, wherein the bonding wire passes through at least one of the separate support structures such that the support structure encloses a portion of the bonding wire on all sides, the at least one of the support structures being monolithic.
2. The multi-chip package of claim 1 , further comprising an interposer disposed between the first chip and the second chip.
3. The multi-chip package of claim 2 , further comprising an insulating tape formed on a bottom surface of the second chip.