IP Library › Granted Patent US 7,298,117
Granted Patent B2
US 7,298,117 · App. 11/362,513 · Granted Nov 20, 2007

Step-up (boost) DC regulator with two-level back-bias switch gate voltage

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,298,117
App. No.
11/362,513
Filed
Feb 27, 2006
Granted
Nov 20, 2007
Kind
B2
Examiner
RILEY, SHAWN
Art Unit
2838
USPC
323/222
Abstract

The invention provides a DC-DC converter capable of being started up in a state in which an input voltage is low and capable of being structured without increasing a circuit size. A back-gate voltage (Vsb) is outputted from a back-gate voltage generating circuit (VBGN), and is inputted to a back gate of a transistor (FET 1 ). During a period during which an output voltage (Vout) is lower than a reference voltage (e 0 ), an oscillation signal (OS 1 ) is inputted to a gate of the transistor (FET 1 ), and the back-gate voltage (Vsb) is set at a grounded voltage. Therefore, the transistor (FET 1 ) has a reference threshold voltage (Vto). On the other hand, during a period during which the output voltage (Vout) is higher than the reference voltage (e 0 ), a pulse signal (PS) is inputted to the gate of the transistor (FET 1 ), and the back-gate voltage (Vsb) is set at an output voltage of a charge pump portion ( 5 ). Therefore, the transistor (FET 1 ) has a threshold voltage higher than the reference threshold voltage (Vto).

Claims (21)

1. A step-up type DC-DC converter comprising:

a main switching transistor that is an N-type conductive element;

a comparator that makes a comparison between a reference voltage and an output voltage and makes a discrimination between a first period during which the output voltage is lower than the reference voltage and a second period during which the output voltage is higher than the reference voltage; and

a back-gate control unit that, in accordance with a comparison result obtained from the comparator, sets a back-gate voltage of the main switching transistor at a first back-gate voltage during the first period, and sets the back-gate voltage thereof at a second back-gate voltage lower than the first back-gate voltage during the second period.

2. The step-up type DC-DC converter according to claim 1 , wherein the reference voltage is a minimum voltage necessary to obtain drive ability of the main switching transistor that satisfies specifications of the DC-DC converter, and is determined in accordance with a back-gate bias effect of the main switching transistor that is fixed by the second back-gate voltage.

3. The step-up type DC-DC converter according to claim 1 , wherein the back-gate control unit comprises:

a first back-gate voltage generating portion that, in accordance with a comparison result obtained from the comparator, supplies a grounded voltage so as to be used as the first back-gate voltage during the first period, and is stopped so as not to be operated during the second period; and

a second back-gate voltage generating portion that, in accordance with a comparison result obtained from the comparator, is stopped so as not to be operated during the first period, and generates a second back-gate voltage during the second period.

4. The step-up type DC-DC converter according to claim 3 , wherein the first back-gate voltage generating portion includes a first switch portion one side of which is grounded, the first switch portion being in an electrically conductive state during the first period and being in an electrically non-conductive state during the second period.

5. The step-up type DC-DC converter according to claim 1 , further comprising:

a first control unit that is operated by a voltage lower than the reference voltage and that performs switching control of the main switching transistor;

a second control unit that is operated by a voltage higher than the reference voltage and that performs switching control of the main switching transistor; and

a second switch portion that, in accordance with a comparison result obtained from the comparator, selects the first control unit during the first period, and selects the second control unit during the second period.

6. The step-up type DC-DC converter according to claim 1 , wherein the main switching transistor includes a first gate and a second gate between which a pair of source/drain are shared; the first control unit, which is operated by a voltage lower than the reference voltage and which performs switching control of the main switching transistor, drives the first gate; and the second control unit, which is operated by a voltage higher than the reference voltage and which performs switching control of the main switching transistor, drives the second gate.

7. The step-up type DC-DC converter according to claim 6 , wherein a size of the first gate is made smaller than that of the second gate.

8. The step-up type DC-DC converter according to claim 6 , wherein the main switching transistor has a multi-gate structure in which a plurality of gates are laid out with respect to a pair of source/drain, and a part of the plurality of gates is assigned as the first gate, whereas the remainder of the plurality of gates is assigned as the second gate.

9. The step-up type DC-DC converter according to claim 4 , wherein the reference voltage is a minimum voltage by which the second control unit can be driven.

10. The step-up type DC-DC converter according to claim 5 , wherein the reference voltage is a minimum voltage by which the second control unit can be driven.

11. A method for controlling a step-up type DC-DC converter, comprising:

a step of making a comparison between a reference voltage and an output voltage and making a discrimination between a first period during which the output voltage is lower than the reference voltage and a second period during which the output voltage is higher than the reference voltage; and

a step of setting a back-gate voltage of a main switching transistor at a first back-gate voltage during the first period and setting the back-gate voltage thereof at a second back-gate voltage lower than the first back-gate voltage during the second period.

Assignments (10)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036036/0738 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
CHANGE OF NAME Recorded Jul 22, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024982/0245 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 12, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021998/0645 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2006
From: HASEGAWA, MORIHITO; OZAWA, HIDEKIYO; TAJIRI, SHOJI; KASAI, TOSHIHIKO
To: FUJITSU LIMITED
Reel/Frame 017780/0204 →
Priority Claims (1)
JP 2005-355404 · Dec 8, 2005 · national
Continuity (1)
Related Publication 20070132435A1 · Jun 14, 2007