IP Library Granted Patent US 7,299,440
Granted Patent B2
US 7,299,440 · App. 10/980,171 · Granted Nov 20, 2007

Semiconductor integrated circuit including standard cell, standard cell layout design method, and layout design software product stored in computer-readable recording medium

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,299,440
App. No.
10/980,171
Granted
Nov 20, 2007
Kind
B2
Abstract

According to the present invention, there is provided a semiconductor integrated circuit layout design method of laying out standard cells by using a layout apparatus including an input unit, an arithmetic unit, and a storage unit, comprising, causing the arithmetic unit to calculate an area necessary for layout of each standard cell by using data about a plurality of kinds of standard cells having different heights in a row direction, which is stored in the storage unit in advance, causing the arithmetic unit to calculate the numbers of stages of row regions having heights corresponding to the standard cells on the basis of the calculated area, and causing the arithmetic unit to lay out the standard cells in the corresponding row regions.

Claims (10)

1. A semiconductor integrated circuit layout design method of laying out standard cells by using a layout apparatus including an input unit, an arithmetic unit, and a storage unit, comprising:

causing the arithmetic unit to calculate an area necessary for layout of each standard cell by using data about a plurality of kinds of standard cells having different heights in a row direction, which is stored in the storage unit in advance;

causing the arithmetic unit to calculate the numbers of stages of row regions having heights corresponding to the standard cells on the basis of the calculated area; and

causing the arithmetic unit to lay out the standard cells in the corresponding row regions.

2. A method according to claim 1 , wherein the plurality of kinds of standard cells having different heights in the row direction have the same function and different driving capabilities in correspondence with the height.

3. A computer-readable medium storing a layout design software product for a semiconductor integrated circuit using standard cells, for use in a layout apparatus including an input unit, an arithmetic unit, and a storage unit, said layout design software product when executed by a computer resulting in performance of steps comprising:

causing the arithmetic unit to calculate an area necessary for layout of each standard cell by using data about a plurality of kinds of standard cells having different heights in a row direction;

calculating the numbers of stages of row regions having heights corresponding to the standard cells on the basis of the calculated area; and

laying out the standard cells in the corresponding row regions.

4. A method according to claim 3 wherein the plurality of kinds of standard cells having different heights in the row direction have the same function and different driving capabilities in correspondence with the height.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2005
From: YOSHIDA, TAKESHI; TAMURA, NAOYUKI; YAMAMOTO, YOU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 016250/0665 →
Priority Claims (1)
JP 2004-057276 · Mar 2, 2004 · national
Continuity (1)
Related Publication 20050198604A1 · Sep 8, 2005