Increasing electromigration lifetime and current density in IC using vertically upwardly extending dummy via
View Patent ↗An integrated circuit with increased electromigration lifetime and allowable current density and methods of forming same are disclosed. In one embodiment, an integrated circuit includes a conductive line connected to at least one functional via, and at least one dummy via having a first, lower end electrically connected to the conductive line and a second upper end electrically unconnected (isolated) to any conductive line. Each dummy via extends vertically upwardly from the conductive line and removes a portion of a fast diffusion path, i.e., metal to dielectric cap interface, which is replaced with a metal to metallic liner interface. As a result, each dummy via reduces metal diffusion rates and thus increases electromigration lifetimes and allows increased current density.
1. An integrated circuit comprising:
a first conductive line connected to a lower end of at least one functional via; and
at least one dummy via having a first, lower end electrically connected to the first conductive line and a second upper end electrically unconnected to any other conductive line,
wherein each dummy via interrupts a metal to diffusion baffler layer interface of the first conductive line to introduce a metal to metallic liner interface,
wherein each dummy via and each functional via extends upwardly from substantially the same plane, and
wherein each dummy via includes a horizontal cross-section of substantially the same size as each functional via.
2. The integrated circuit of claim 1 , wherein each dummy via is fully landed on the conductive line.
3. The integrated circuit of claim 1 , wherein the at least one dummy via is placed on the conductive line such that the dummy via extends beyond a width of the conductive line.
4. The integrated circuit of claim 3 , wherein the at least one dummy via has a substantially circular cross-section in a horizontal direction.
5. The integrated circuit of claim 3 , wherein the at least one dummy via has an elongated cross-section in a horizontal direction.
6. The integrated circuit of claim 5 , wherein the elongated cross-section has a length to width ratio of approximately 2:1 in the horizontal direction.
7. The integrated circuit of claim 5 , wherein the length extends across the conductive line.
8. The integrated circuit of claim 5 , wherein the length extends along the conductive line.
9. The integrated circuit of claim 1 , wherein the at least one dummy via includes a plurality of dummy vias.
10. The integrated circuit of claim 9 , wherein each dummy via is spaced from an adjacent dummy via on an order of no less than approximately 1 μm and no greater than approximately 100 μm.
11. The integrated circuit of claim 9 , wherein the plurality of dummy vias are spaced evenly along the conductive line.
12. The integrated circuit of claim 1 , wherein each dummy via extends through a dielectric cap that extends over the conductive line and a dielectric layer in which the conductive line is embedded.
13. An integrated circuit comprising:
a first conductive line connected to a lower end of at least one functional via, the at least one functional via being electrically connected to at least one other conductive line; and
at least one dummy via electrically connected to the conductive line and extending vertically upwardly from the conductive lines,
wherein each dummy via interrupts a metal to diffusion barrier layer interface of the first conductive line to introduce a metal to metallic liner interface,
wherein each dummy via and each functional via extends upwardly from substantially the same plane,
wherein each dummy via includes a horizontal cross-section of substantially the same size as each functional via, and
wherein each dummy via is electrically isolated from any other conductive line.
14. The integrated circuit of claim 13 , wherein each dummy via is one of: fully landed on the conductive line and placed on the conductive line such that the dummy via extends beyond a width of the conductive line.
15. The integrated circuit of claim 13 , wherein the at least one dummy via has a cross-sectional shape in the horizontal direction substantially in the form of one of: a circle and an oval.
16. The integrated circuit of claim 13 , wherein the at least one dummy via includes a plurality of dummy vias spaced evenly along the conductive line.
17. The integrated circuit of claim 13 , wherein each dummy via extends through a diffusion barrier layer that extends over the conductive line.