Dot clock synchronization generator circuit
A circuit which generates a dot clock synchronized to an external video signal which can ensure a pulse width allowed by a device which is supplied with the dot clock. A high frequency clock is divided to generate a first dot clock, and the phase is initialized in accordance with information on a previously set frequency division ratio upon detection of a significant edge of a horizontal synchronization signal. Also, a second dot clock, the logical level of which changes every minimum allowable period, is formed from the high frequency clock in accordance with information on a previously set minimum allowable period, and the phase is modified upon detection of the significant edge such that the minimum allowable period is ensured for the logical level period even before and after the detection. The second dot clock is selected upon detection of the significant edge, and afterwards, the first dot clock is selected when a confirmation can be made that the timing of the first dot clock is coincident with or behind the timing of the second dot clock.
1. A dot clock synchronization generator circuit for generating a dot clock corresponding to each pixel on one horizontal scanning line based on a horizontal synchronization signal applied thereto, and a high frequency signal applied thereto having a frequency higher than the frequency of the dot clock to be generated, said dot clock synchronization generator circuit comprising:
a frequency division ratio storing part for storing information on a frequency division ratio for diving the high frequency clock;
a minimum allowable period information storing part for storing information on a minimum allowable period of each logical level period of the dot clock, defined by the number of cycles of the high frequency clock;
an edge detecting part for detecting a significant edge of the horizontal synchronization signal;
a first dot clock forming part for dividing the high frequency clock to form a first dot clock in accordance with the information on the frequency division ratio stored in said frequency division ratio storing part, and for initializing the phase of the first dot clock in accordance with the information on the frequency division ratio stored in said frequency division ratio storing part upon detection of the significant edge of the horizontal synchronization signal;
a second dot clock forming part for forming a second dot clock from the high frequency clock in accordance with the information on the minimum allowable period stored in said minimum allowable period information storing part, said second dot clock changing a logical level every minimum allowable period, and for modifying the phase of the second dot clock upon detection of the significant edge of said horizontal synchronization signal such that the minimum allowable period of the logical level period is ensured even before and after the detection of the significant edge;
a selecting part for selecting one of the first and second dot clocks as a dot clock to be output; and
a selection control part for forcing said selecting part to select the second dot clock from said second dot clock forming part upon detection of the significant edge of the horizontal synchronization signal, and for forcing said selecting part to select the first dot clock from said first dot clock forming part when a confirmation can be made that the timing of the significant edge of the first dot clock is coincident with or behind the timing of the significant edge of the second dot clock.
2. A dot clock synchronization generator circuit according to claim 1 , wherein said all parts are formed on the same semiconductor chip.
3. A dot clock synchronization generator circuit according to claim 1 , wherein said frequency division ratio information storing part is capable of variably setting the information on the frequency division ratio.
4. A dot clock synchronization generator circuit according to claim 2 , wherein said frequency division ratio information storing part is capable of variably setting the information on the frequency division ratio.
5. A dot clock synchronization generator circuit according to claim 1 , wherein said minimum allowable period storing part is capable of variably setting the information on the minimum allowable period.
6. A dot clock synchronization generator circuit according to claim 2 , wherein said minimum allowable period storing part is capable of variably setting the information on the minimum allowable period.
7. A dot clock synchronization generator circuit according to claim 3 , wherein said minimum allowable period storing part is capable of variably setting the information on the minimum allowable period.
8. A dot clock synchronization generator circuit according to claim 4 , wherein said minimum allowable period storing part is capable of variably setting the information on the minimum allowable period.
9. A dot clock synchronization generator circuit according to any of claims 1 - 8 , wherein said frequency division ratio storing part stores the number of cycles of the high frequency clock equivalent to one period of the dot clock, as the frequency division ratio information.
10. A dot clock synchronization generator circuit according to any of claims 1 - 8 , wherein said frequency division ratio information storing part stores timing information for starting each logical level period of the first dot clock, and timing information for initializing as the phase of the first dot clock upon detection of the significant edge of the horizontal synchronization signal as the frequency division ratio information.