IP Library › Granted Patent US 7,351,641
Granted Patent B2
US 7,351,641 · App. 11/201,726 · Granted Apr 1, 2008

Structure and method of forming capped chips

Assignee: Tessera, Inc.
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Quick Facts
Patent No.
US 7,351,641
App. No.
11/201,726
Granted
Apr 1, 2008
Kind
B2
Abstract

As disclosed herein, structures and methods are provided for forming capped chips. As provided by the disclosed method, a metal base pattern is formed on a chip insulated from wiring of the chip, and a cap is formed including a metal. The cap is joined to the metal base pattern on the chip to form the capped chip. In one embodiment, a front surface of the chip is exposed which extends from a contact of the chip to an edge of the chip. In another embodiment, a conductive connection is formed to the contact, the conductive connection extending from the contact to a terminal at an exposed plane above the front surface of the chip.

Claims (38)

1. A method of forming a capped chip, said method comprising:

forming a metal base pattern on a front surface of a chip;

forming a cap, including:

providing a mandrel having a depression formed in a surface thereof,

applying an insulating coating atop said surface of said mandrel,

removing a portion of said insulating coating to expose a region of said surface, the exposed region including the depression, and

forming a metal layer atop only the exposed region of said surface including the depression; and

joining said cap to said metal base pattern on said chip to form a capped chip such that said front surface of said chip remains uncovered from at least a contact of said chip to a peripheral edge of said chip.

2. A method as claimed in claim 1 , further comprising: forming a conductive contact to said contact of said chip, said conductive contact extending vertically from said contact of said chip to provide a contact surface at an exposed plane that is located above said front surface of said chip.

3. The method of claim 1 , further comprising: removing, after joining said cap to said metal, said mandrel to expose said front surface from said contact to said peripheral edge of said chip.

4. The method of claim 3 , wherein said mandrel includes a low adhesion metal, and said removing step includes applying a force to separate said mandrel from said cap.

5. The method of claim 1 , wherein said step of forming said cap includes concurrently forming a plurality of said caps, arranged in an array, on said mandrel, and said joining step includes disposing said plurality of said caps over an area encompassing a plurality of said chips, and concurrently joining said plurality of chips said plurality of caps to form a plurality of said capped chips.

6. A method of forming an assembly, said method comprising:

forming a capped chip according to a method as claimed in claim 1 ;

providing an encapsulant over said front surface of said chip; and

providing a conductive connector extending between said contact of said capped chip and a top surface of said encapsulant.

7. A method of forming an assembly, said method comprising:

forming a capped chip according to a method as claimed in claim 1 ; and

conductively interconnecting said contact of said capped chip to a microelectronic element disposed above said capped chip.

8. A method as claimed in claim 7 , wherein said microelectronic element includes at least one selected from the group consisting of a chip carrier, a circuit panel, a lead frame, and a substrate.

9. The method of claim 1 , wherein said coating is an insulating coating, and said step of forming said metal layer includes electroplating said metal atop the exposed region of said mandrel.

10. The method of claim 1 , wherein said step of forming said metal layer includes forming a first metal layer atop the exposed region of said mandrel, and forming a second metal layer atop said first metal layer.

11. The method of claim 1 , wherein said joining step includes heating said mandrel and said chip to a desired temperature, and said mandrel and said chip have substantially same coefficients of thermal expansion (CTE).

12. The method of claim 1 , wherein said joining step includes heating said mandrel and said chip to a desired temperature, said mandrel and said chip have different coefficients of thermal expansion (CTE), and said mandrel is sized such that said cap is aligned with said chip at the desired temperature.

13. The method of claim 1 , wherein said joining step includes heating said mandrel and said chip to a desired temperature, said mandrel and said cap having different coefficients of thermal expansion (CTE) such that said mandrel separates from said metal layer while cooling down after said heating step is carried out.

14. A method of forming a capped chip, said method comprising:

forming a respective metal base pattern on a front surface of each one of a plurality of chips, said plurality of chips being arranged according to a given array;

patterning a metal sheet to form a cap frame that includes a plurality of caps, arranged according to the given array; and

concurrently joining each one of said plurality of caps to corresponding ones of said plurality of chips to form a plurality of capped chips such that the front surface of each one of a plurality of chips remains uncovered from at least a contact of that chip to a peripheral edge of that chip.

15. The method of claim 14 , further comprising: severing said plurality of capped chips from said cap frame concurrently with severing said plurality of chips.

16. A method of forming an assembly, said method comprising:

forming a plurality of capped chips according to a method as claimed in claim 14 ;

providing an encapsulant over a front surface of said plurality of capped chips; and

providing a conductive connector extending between said contact of each chip and a top surface of said encapsulant.

17. A method of forming an assembly, said method comprising:

forming a plurality of capped chips according to a method as claimed in claim 14 ; and

conductively interconnecting said contact of each capped chip to an associated microelectronic element disposed above that chip.

18. A method as claimed in claim 17 , wherein said microelectronic element includes at least one selected from the group consisting of a chip carrier, a circuit panel, a lead frame, and a substrate.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 26, 2005
From: HABA, BELGACEM; BEROZ, MASUD; URBISH, GLENN; TUCKERMAN, DAVID B.
To: TESSERA, INC.
Reel/Frame 016841/0155 →
Continuity (2)
Provisional Application 6060090800 · Aug 12, 2004
Related Publication 20060033189A1 · Feb 16, 2006