High speed array pipeline architecture
A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline.
1. A memory device, comprising: a memory array having a plurality of memory cells; and a plurality of peripheral devices for reading data out of and writing data into said memory array, said peripheral devices comprising: a first write driver connected to a first input/output line, said first input/output line being associated with a digitline connected to certain of said plurality of memory cells; a first read amplifier connected to said first input/output line; a first input/output device responsive to a first column select signal for connecting said first input/output line to said digitline; a second write driver connected to a second input/output line, said second input/output line being associated with said digitline; a second read amplifier connected to said second input/output line; and a second input/output device responsive to a second column select signal for connecting said second input/output line to said digitline.
2. The memory device of claim 1 wherein said peripheral devices further include at least one of a decoder, a p-sense amplifier, an n-sense amplifier, an isolation circuit, and an equalization circuit.
3. The memory device of claim 2 wherein said decoder is operable to generate said first and second column select signals in response to a first column decode toggle signal, a second decode toggle signal, a column address signal, and a column enable signal.
4. The memory device of claim 1 wherein said first and second input/output devices are transistors.
5. The memory device of claim 1 wherein said first and second write drivers and said first and second read amplifiers are connected to at least one tri-state read/write data line.
6. A memory system, comprising: a memory controller; a memory device, said memory device comprising: a memory array having a plurality of memory cells; a plurality of peripheral devices for reading data out of and writing data into said memory array, said peripheral devices comprising: a first write driver connected to a first input/output line, said first input/output line being associated with a digitline connected to certain of said plurality of memory cells; a first read amplifier connected to said first input/output line; a first input/output device responsive to a first column select signal for connecting said first input/output line to said digitline; a second write driver connected to a second input/output line, said second input/output line being associated with said digitline; a second read amplifier connected to said second input/output line; and a second input/output device responsive to a second column select signal for connecting said second input/output line to said digitline; and a system bus interconnecting said memory controller and said memory device.
7. The memory system of claim 6 wherein said peripheral devices further include at least one of a decoder for generating said first and second column select signals, a p-sense amplifier, an n-sense amplifier, an isolation circuit, and an equalization circuit.
8. The memory system of claim 7 wherein said decoder is operable to generate said first and second column select signals in response to a first column decode toggle signal, a second decode toggle signal, a column address signal, and a column enable signal.
9. The memory system of claim 6 wherein said first and second input/output devices are transistors.
10. The memory system of claim 6 wherein said first and second write drivers and said first and second read amplifiers are connected to a tri-state read/write data line.
11. A computing system, comprising: a processor; an input device in communication with said processor for receiving data and instructions for operating said computing system; an output device in communication with said processor for displaying and outputting data generated by said processor; a data storage device in communication with said processor for storing software and data sets for use by said processor; and a memory system in communication with said processor, said memory system comprising: a memory controller; a memory device, said memory device comprising: a memory array having a plurality of memory cells; a plurality of peripheral devices for reading data out of and writing data into said memory array, said peripheral devices comprising: a first write driver connected to a first input/output line, said first input/output line being associated with a digitline connected to certain of said plurality of memory cells; a first read amplifier connected to said first input/output line; a first input/output device responsive to a first column select signal for connecting said first input/output line to said digitline; a second write driver connected to a second input/output line, said second input/output line being associated with said digitline; a second read amplifier connected to said second input/output line; and a second input/output device responsive to a second column select signal for connecting said second input/output line to said digitline; and a system bus interconnecting said memory controller and said memory device.
12. The computing system of claim 11 wherein said peripheral devices further include at least one of a decoder for generating said first and second column select signals, a p-sense amplifier, an n-sense amplifier, an isolation circuit, and an equalization circuit.
13. The computing system of claim 1 wherein said decoder is operable to generate said first and second column select signals in response to a first column decode toggle signal, a second decode toggle signal, a column address signal, and a column enable signal.
14. The computing system of claim 11 wherein said first and second input/output devices are transistors.
15. The computing system of claim 11 wherein said first and second write drivers and said first and second read amplifiers are connected to a tri-state read/write data line.
16. A memory device of the type comprising a memory array having a plurality of memory cells, said memory cells being accessed via a plurality of digitline pairs, the improvement comprising each of said plurality of digitline pairs being associated with first and second read drivers, said drivers connected to said digitline pair through first and second input/output devices responsive to separate control signals.
17. The memory device of claim 16 wherein each of said separate control signals are the semi-independent of one another.
18. The memory device of claim 16 wherein each of said digitline pairs is further associated with first and second write drivers.
19. The memory device of claim 16 wherein each of said digitlines is further associated with two or more read sense-amplifiers and drivers.