IP Library Granted Patent US 7,353,300
Granted Patent B2
US 7,353,300 · App. 11/407,447 · Granted Apr 1, 2008

Apparatus to improve the firmware efficiency for a multiframe serial interface

Assignee: Atmel Corporation
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Quick Facts
Patent No.
US 7,353,300
App. No.
11/407,447
Filed
Apr 19, 2006
Granted
Apr 1, 2008
Kind
B2
Art Unit
2181
USPC
710/30
Abstract

A serial network controller contains control logic to analyze and determine a duration of a proper frame time slot. A number of data fields in a transmission is ascertained from an identifier field supplied in a header field. The number of data fields plus a margin for data framing overhead is calculated to determine the frame time slot duration. A timer is programmed with the calculated frame time slot duration. The timer is clocked at each bit period of the transmission until the calculated duration of the frame time slot is reached. At the frame time slot value, a transmit ready flag is unmasked, allowing termination of the frame with a proper margin. By managing frame time slot calculation, timer operations, and interrupt handling, the control logic relieves a microprocessor core and other system resources from network timing details. The control logic frees system resources for other applications.

Claims (43)

1. A multiframe bus management device comprising:

a frame bit counter capable of counting a plurality of frame bit periods and producing a tally of the plurality of frame bit periods counted during a message length;

a comparator coupled to the frame bit counter, the comparator capable of comparing a frame bit quota with the tally of the plurality of frame bit periods and producing a compare signal; and

a set/reset logic block coupled to the comparator, the set/reset logic block capable of retaining a value of the compare signal and producing an unmasking signal.

2. The multiframe bus management device of claim 1 , wherein the compare signal is produced by the comparator when the tally of the plurality of frame bit periods equals the frame bit quota.

3. The multiframe bus management device of claim 1 , wherein the unmasking signal is produced by an assertive value of the compare signal.

4. The multiframe bus management device of claim 1 , wherein the frame bit quota acts proportionally to the message length.

5. The multiframe bus management device of claim 1 , wherein the set/reset logic block is coupled to a signal masking block capable of receiving the unmasking signal and propagating a masked signal.

6. The multiframe bus management device of claim 1 , wherein the unmasking signal produces an interrupt, to a transmission managing application, signaling that a present message transmission is concluded.

7. The multiframe bus management device of claim 1 , wherein the device is capable of processing a Local Interconnect Network (LIN) protocol.

8. A multiframe bus management device comprising:

a frame bit counter capable of counting a plurality of frame bit periods and producing a tally of the plurality of frame bit periods counted during a message length;

a finite state machine coupled to the frame bit counter and capable of extracting a frame bit quota from a message content;

a comparator coupled to the frame bit counter and the finite state machine, the comparator configured to compare the frame bit quota with the tally and produce a compare signal; and

a set/reset logic block coupled to the comparator and the finite state machine, the set/reset logic block capable of retaining a value of the compare signal and producing a unmasking signal.

9. The multiframe bus management device of claim 8 , wherein the compare signal is produced by the comparator when the tally of the plurality of frame bit periods equals the frame bit quota.

10. The multiframe bus management device of claim 8 , wherein the unmasking signal is produced by an assertive value of the compare signal.

11. The multiframe bus management device of claim 8 , wherein the frame bit quota is proportional to the message length.

12. The multiframe bus management device of claim 8 , wherein the set/reset logic block is coupled to a signal masking block capable of receiving the unmasking signal and propagating a masked signal.

13. The multiframe bus management device of claim 8 , wherein the unmasking signal produces an interrupt, to a transmission managing application, signaling that a present message transmission is concluded.

14. The multiframe bus management device of claim 8 , wherein the finite state machine resets the set/reset logic block, the frame bit counter, and the comparator at a conclusion of a message.

15. The multiframe bus management device of claim 8 , wherein the device is capable of processing a Local Interconnect Network (LIN) protocol.

16. A multiframe bus management device comprising:

a counting means for counting a plurality of frame bit periods and producing a tally of frame bit periods counted in a message;

a controlling means for managing a bus transmission of the message and extracting a frame bit quota from the message;

a comparing means, coupled to the counting means and the controlling means, for comparing the tally with the frame bit quota and producing a compare signal; and

a set/reset means, coupled to the comparing means, for receiving the compare signal and generating a unmasking signal.

17. The multiframe bus management device of claim 16 , further comprising a masking means for receiving the unmasking signal and unmasking a signal.

18. The multiframe bus management device of claim 16 , wherein the device is capable of processing a Local Interconnect Network (LIN) protocol.

19. A process for managing a serial network interface comprising:

receiving a frame bit quota proportional to a duration of a network message;

counting a plurality of frame bit periods in a message transmission;

comparing for an equality between a count of the plurality of frame bit periods and the frame bit quota; and

unmasking a signal if the step of comparing produces an equality.

20. The process for managing a serial network interface of claim 19 , further comprising interrupting a software application to signal a present message transmission is concluded.

21. A process for managing a serial network interface comprising:

receiving a specification of a duration of a message in a network transmission;

prescribing a frame bit quota equal to the message duration;

counting a plurality of frame bit periods in a message transmission;

producing a tally of the plurality of frame bit periods counted;

comparing the tally of the plurality of frame bit periods with the frame bit quota;

producing a compare signal if the tally of the plurality of frame bit periods is equal to the frame bit quota; and

unmasking a signal if the compare signal is produced.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2006
From: SCHUMACHER, FREDERIC
To: ATMEL CORPORATION
Reel/Frame 018131/0972 →
Priority Claims (1)
FR 06 00455 · Jan 18, 2006 · national
Continuity (1)
Related Publication 20070168580A1 · Jul 19, 2007