IP Library Granted Patent US 7,354,849
Granted Patent B2
US 7,354,849 · App. 11/365,082 · Granted Apr 8, 2008

Catalytically enhanced atomic layer deposition process

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,354,849
App. No.
11/365,082
Granted
Apr 8, 2008
Kind
B2
Abstract

A method for carrying out a damascene process to form an interconnect comprises providing a semiconductor substrate having a trench etched into a dielectric layer, wherein the trench includes a barrier layer and an adhesion layer, depositing a copper seed layer onto the adhesion layer using an ALD process, depositing an iodine catalyst layer onto the copper seed layer using an ALD process, and depositing a copper layer onto the copper seed layer using an ALD process. The iodine catalyst layer causes the copper layer to fill the trench by way of a bottom-up fill mechanism. The trench fill is performed using a single ALD process, which minimizes the creation of voids and seams in the final copper interconnect.

Claims (29)

1. A method comprising:

providing a semiconductor substrate having a trench etched into a dielectric layer, wherein the trench includes a barrier layer and an adhesion layer; and

performing a catalytically enhanced atomic layer deposition process that comprises:

pulsing a first copper precursor to form a copper seed layer on the adhesion layer;

pulsing an iodine precursor to form an iodine catalyst layer on the copper seed layer; and

pulsing a second copper precursor to form a copper layer on the copper seed layer that fills the trench by way of a bottom-up fill mechanism due to the iodine catalyst layer;

wherein the first and second copper precursors are selected from the group consisting of Cu(acac) 2 (where acac=acetylacetonato), Cu(thd) 2 (where thd=tetrahydrodionato), CpCu(CNMe), CpCu(CNCMe 3 ), Cp*CuCO, CpCuPR 3 (where R=Me, Et, or Ph), CpCu(CSiMe 3 ) 2 , MeCu(PPh 3 ) 3 , CuMe, CuCCH (ethynylcopper), CuCMe 3 (methylacetylidecopper), (H 2 C═CMeCC)Cu (3-methyl-3-buten-1-ynylcopper), (MCH 2 CH 2 CC)Cu (1-pentynylcopper), CuCCPh, C 6 H 5 Cu (phenyl copper), (ME) 3 CCCCu (3,3-dimethyl-1-butynyl)copper, (H 3 CCH═CH) 2 CuLi, Me 3 SiCCCH 2 Cu, CuCN, [Cu(OAc)]n (where OAc=acetate), Cu 2 Cl 2 (butadiene), μ-[(trimethylsilyl)methyl]copper, C 7 H 7 CuO(2-methoxyphenylcopper), ([COD]CuCl) 2 , (MeCN) 4 CuX (where X=a halide, an alkyl, an amine, or a phenyl group), Me 3 SiOCu(PMe 3 ) 3 , Cu(C 4 H 4 S), and a Cu-carbene compound, and

wherein the iodine precursor is selected from the group consisting of an iodine gas, an iodine plasma, l 2 , C 2 H 5 l, C 2 H 3 1, CH 3 l, CH 2 12, and CHl 3 .

2. The method of claim 1 , further comprising planarizing the copper layer.

3. The method of claim 1 , wherein the barrier layer and the adhesion layer are formed using ALD processes.

4. A method comprising:

providing a semiconductor substrate having a trench etched into a dielectric layer;

placing the semiconductor substrate within a reaction chamber;

pulsing a barrier layer precursor into the reaction chamber, wherein the barrier layer precursor reacts to form a barrier layer within the trench;

pulsing an adhesion layer precursor into the reaction chamber, wherein the adhesion layer precursor reacts to form an adhesion layer atop the barrier layer;

pulsing a first copper precursor into the reaction chamber, wherein the first copper precursor reacts to form a copper seed layer atop the adhesion layer;

pulsing a catalyst into the reaction chamber, wherein the catalyst forms a catalyst layer that favors collecting on a bottom surface of the trench; and pulsing a second copper precursor into the reaction chamber, wherein the catalyst layer causes the second copper precursor to react and fill the trench with a copper layer by way of a bottom-up fill mechanism;

wherein the first and second copper precursors are selected from the group consisting of Cu(acac) 2 (where acac=acetylacetonato), Cu(thd) 2 (where thd tetrahydrodionato), CpCu(CNMe), CpCu(CNCMe 3 ), Cp*CuCO, CpCuPR 3 (where R=Me, Et, or Ph), CpCu(CSiMe 3 ) 2 , MeCu(PPh 3 ) 3 , CuMe, CuCCH (ethynylcopper), CuCMe 3 (methylacetylidecopper), (H 2 C═CMeCC)Cu (3-methyl-3-buten-1-vnylcopper), (MCH 2 CH 2 CC)Cu (1-pentyvylcopper), CuCCPh, C 6 H 5 Cu (phenyl copper), (ME) 3 CCCCu (3,3-dimethvl-1-butynyl)copper, (H 3 CCH═CH) 2 CuLi, Me 3 SiCCCH 2 Cu, CuCN, n (where OAc=acetate), Cu 2 Cl 2 (butadiene), μ-copper, C 7 H 7 CuO(2-methoxyphenylcopper), (CuCl) 2 , (MeCN) 4 CuX (where X=a halide, an alkyl, an amine, or a phevyl group), Me 3 SiOCu(PMe 3 ) 3 , Cu(C 4 H 4 S), and a Cu-carbene compound.

5. The method of claim 4 , wherein the barrier layer precursor comprises tantalum and nitrogen.

6. The method of claim 4 , wherein the adhesion layer precursor comprises tantalum or ruthenium.

7. The method of claim 4 , wherein the catalyst comprises iodine.

8. The method of claim 7 , wherein the pulsing of the catalyst comprises pulsing an iodine precursor into the reaction chamber, wherein the iodine precursor reacts to form the catalyst layer.

9. The method of claim 8 , wherein the iodine precursor comprises I 2 , C 2 H 5 l, C 2 H 3 1, CH 3 l, CH 2 I 2 , or CHl 3 .

10. The method of claim 4 , wherein the catalyst comprises bromine.

11. The method of claim 10 , wherein the pulsing of the catalyst comprises pulsing a bromine precursor into the reaction chamber, wherein the bromine precursor reacts to form the catalyst layer.

12. The method of claim 11 , wherein the bromine precursor comprises Br2, CH 3 Br, or C 2 H 5 Br.

13. The method of claim 4 , wherein the catalyst comprises a catalytic metal.

14. The method of claim 13 , wherein the catalytic metal comprises indium acetate, indium acetylacetonate, indium (III) chloride, indium (III) bromide, indium (III) iodide, trimethylindium, tin hydride (SnH 4 ), tin acetate, tetraethyltin, or tin acetylacetonate.

15. The method of claim 4 , wherein the pulsing of the barrier layer precursor, the pulsing of the adhesion layer precursor, the pulsing of the first copper precursor, the pulsing of the catalyst, and the pulsing of the second copper precursor are all performed without removing the semiconductor substrate from the reaction chamber.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 3, 2014
From: PLOMBON, JOHN J.; LAVOIE, ADRIEN R.; DOMINGUEZ, JUAN E.; HAN, JOSEPH H.; SIMKA, HARSONO S.
To: INTEL CORPORATION
Reel/Frame 033890/0171 →
Continuity (1)
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