Semiconductor manufacturing apparatus for modifying-in-film stress of thin films, and product formed thereby
An apparatus for depositing a thin film on a substrate and product produced thereby are disclosed. In particular, deposition of the thin film is carried out on the substrate having an applied pressure. This applied pressure flexes the substrate to reduce in-plane stresses, wherein removal of the applied pressure after deposition of the thin film modifies the in-film stress for the thin film. With the above-described arrangement, it is possible to minimize the deterioration of electric characteristics of a semiconductor device and the occurrence of defects, such as film delamination, substrate cracks, and the like.
1. A substrate bearing a thin film of a material having a modified in-film stress, said substrate having a predetermined stress wherein said predetermined stress provides a mechanical stress s to said thin film, said mechanical stress being derived using the following equations:
s=s i +s T (1)
where s i is intrinsic stress calculated by the expression:
s i =[E s /6(1− n s )]( d s 2 /d f )(1 /R s −1 /R f ) (2)
where E s and n s are Young's modulus and Poisson ratio of said substrate, respectively, d s and d f are thickness of said substrate and said thin film, respectively, and R s and R f are radii of curvature of said substrate without and with said thin film, respectively, and where s T is thermal stress in said thin film calculated by the expression:
s T [E f /(1− n f )]( a f −a s )( T d −T M ) (3)
where E f and n f are Young's modulus and Poisson ratio for said thin film, respectively, a f and a s are average thermal coefficients of said thin film and said substrate, and T d and T M are film deposition temperature and temperature during stress measurement, respectively.
2. The substrate as recited by claim 1 , wherein said material is a barrier material.
3. The substrate as recited by claim 1 , wherein said material is a barrier material selected from the group consisting of Ti, TiW, TiN, TaN, Ta-based materials, WN, MoN, AlN, CrN, ScN, barrier metals, barrier metal alloys, and combinations thereof.
4. The substrate as recited by claim 1 , wherein said thin film is a monolayer of said material on said substrate.
5. The substrate as recited by claim 1 , wherein said substrate is a silicon substrate.
6. The substrate as recited by claim 1 , wherein said substrate is a doped silicon substrate, wherein said thin film was disposed over the substrate when preloaded with a tensile stress.
7. A semiconductive device comprising the substrate of claim 1 , wherein said substrate is a silicon substrate.
8. A semiconductive device comprising the substrate of claim 1 , wherein said material is a barrier material.
9. A semiconductive device comprising the substrate of claim 1 , wherein said material is a barrier material selected from the group consisting of Ti, TiW, TiN, TaN, Ta-based materials, WN, MoN, AlN, CrN, ScN, barrier metals, barrier metal alloys, and combinations thereof.
10. A semiconductive device comprising the substrate of claim 1 , wherein said thin film is a monolayer of said material on said substrate.
11. A semiconductive device comprising the substrate of claim 1 , wherein said substrate is a silicon substrate, and said material is a barrier material.
12. A memory device comprising the substrate of claim 1 .
13. A memory device comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate.
14. A memory device comprising the substrate of claim 1 , wherein said material is a barrier material.
15. A memory device comprising the substrate of claim 1 , wherein said material is a barrier material selected from the group consisting of Ti, TiW, TiN, TaN, Ta-based materials, WN, MoN, AlN, CrN, ScN, barrier metals, barrier metal alloys, and combinations thereof.
16. A memory device comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate, and said material is a barrier film.
17. A memory device comprising the substrate of claim 1 , wherein said thin film is a monolayer of said material on said substrate.
18. A memory device comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate, wherein said thin film was disposed over the substrate when preloaded with a tensile stress.
19. A memory device comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate having field oxide areas and drain regions and source regions, and said material is a barrier film, said memory device further comprising transistor gate members, including a wordline bounded by insulative material, formed on a surface of the substrate.
20. A DRAM cell, comprising the substrate of claim 1 .
21. A DRAM cell comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate having field oxide areas, drain regions, and source regions.
22. A DRAM cell comprising the substrate of claim 1 , and transistor gate members formed on a surface of the substrate.
23. A DRAM cell comprising the substrate of claim 1 , transistor gate members formed on a surface of the substrate, and a wordline bounded by insulative material.
24. A DRAM cell comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate having oxide areas, said DRAM cell further comprising transistor gate members formed on a surface of the substrate, wherein said thin film was disposed over the substrate, the oxide areas, and the transistor gate members when preloaded with a tensile stress.
25. A DRAM cell comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate having field oxide areas, drain regions, and source regions, said DRAM cell further comprising transistor gate members formed on a surface of the substrate, and a wordline bounded by insulative material, wherein said thin film was disposed over the substrate, the oxide areas, and the transistor gate members when preloaded with a tensile stress, said thin film having bitline contacts contacting the source regions for electrical communication with a bitline, and, further, having capacitor contacts contacting the drain regions for electrical communication with capacitors.
26. A DRAM cell comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate.
27. A DRAM cell comprising the substrate of claim 1 , wherein said material is a barrier material.
28. A DRAM cell comprising the substrate of claim 1 , wherein said material is a barrier material selected from the group consisting of Ti, TiW, TiN, TaN, Ta-based materials, WN, MoN, AlN, CrN, ScN, barrier metals, barrier metal alloys, and combinations thereof.
29. A DRAM cell comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate, and said material is a barrier film.
30. A DRAM cell comprising the substrate of claim 1 , wherein said thin film is a monolayer of said material on said substrate.
31. A DRAM cell comprising the substrate of claim 1 , wherein said substrate is a doped silicon substrate, wherein said thin film was disposed over the substrate when preloaded with a tensile stress.
32. An apparatus for providing the substrate of claim 1 , said apparatus comprising:
a chamber in which the substrate can be contained;
a sample holder adapted to support the substrate within said chamber; and
a tool for flexing the substrate when supported by said sample holder in order to provide said predetermined stress.
33. The apparatus as recited by claim 32 , wherein said tool comprises a retractable pin.
34. The apparatus as recited by claim 32 , wherein said tool comprises movable clips and a pin.
35. The apparatus as recited by claim 32 , wherein said tool comprises movable clips.
36. The apparatus as recited by claim 32 , wherein said tool comprises a port in the sample holder to apply a vacuum to a backside of the substrate, and movable clips to raise the perimeter of the substrate.
37. The apparatus as recited by claim 32 , wherein said apparatus is adapted to provide said material when the substrate is in said chamber and provided with said predetermined stress by said tool.
38. The apparatus as recited by claim 32 , wherein said apparatus is adapted to deposit said material when the substrate is in said chamber and provided with said predetermined stress by said tool, and wherein said material is a barrier material.
39. The apparatus as recited by claim 32 , wherein said apparatus is adapted to deposit said material when the substrate is in said chamber and provided with said predetermined stress by said tool, and wherein said material is a barrier material selected from the group consisting of Ti, TiW, TiN, TaN, Ta-based materials, WN, MoN, AlN, CrN, ScN, barrier metals, barrier metal alloys, and combinations thereof.
40. The apparatus as recited by claim 32 , wherein said apparatus is adapted to provide said material to the substrate when the substrate is in said chamber and provided with said predetermined stress by said tool, and wherein said thin film is a monolayer of said material on the substrate.