Data strobe synchronization circuit and method for double data rate, multi-bit writes
A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.
1. A method of capturing data in a storage device, the method comprising:
generating a first data strobe pulse responsive to a first global strobe pulse, the first data strobe pulse causing a first storage device to capture a first set of data;
generating a second data strobe pulse responsive to the first data strobe pulse and an active write command; and
in response to the second data strobe pulse, preventing the first storage device from capturing a second set of data.
2. The method of claim 1 wherein the first storage device comprises a flip flop.
3. The method of claim 1 wherein preventing the first storage device from capturing a second set of data comprises disabling a logic circuit.
4. The method of claim 1 wherein the second set of data is a noise pulse.
5. The method of claim 1 further comprising the second data strobe pulse causing a second storage device to capture a second set of data.
6. A method of toggling between logic circuits comprising:
enabling a first write control signal;
generating a first data strobe pulse in response to a first data strobe signal;
in response to the first data strobe pulse, enabling a first logic circuit;
enabling a second write control signal;
while the second write control signal remains enabled, generating a second data strobe pulse in response to a second data strobe signal; and
in response to the second data strobe pulse enabling a second logic circuit.
7. The method of claim 6 wherein in response to the second data strobe pulse further comprises disabling the first logic circuit.
8. The method of claim 6 further comprising capturing data to at least one storage device when the write control signal is enabled.
9. The method of claim 6 wherein the first and second data strobe signals are generated in response to a global data signal respectively.
10. The method of claim 6 wherein the first data strobe signal causes data to be latched to a first storage device and the second data strobe signal causes data to be latched to a second storage device.
11. A method of preventing noise pulses from toggling a logic circuit comprising:
latching data to a first storage device in response to each of a plurality of global data strobe pulses;
in response to a first active write command, discontinuing to latch data to the first storage device and latching data to a second storage device in response to a respective global data strobe pulse.
12. The method of claim 11 wherein at least one of the plurality of global data strobe pulses comprises a noise signals.
13. The method of claim 12 further comprising in response to a second active write command, discontinuing to latch data to the second storage device.
14. The method of claim 11 wherein the first and second storage device comprises a first and second flip flop respectively.
15. A method of storing data in a memory device, the method comprising:
saving data responsive to each transition of a data strobe signal;
in response to receiving a first memory control signal, discarding all of the saved data except for the data saved responsive to a predetermined number of transitions of the data strobe signal received prior to the first memory control signal; and
storing the saved data that was not discarded in the memory device.
16. The method of claim 15 , further comprising storing data in the memory device responsive to each transition of the data strobe signal occurring after the first memory control signal is received.
17. The method of claim 16 wherein the act of storing data in the memory device responsive to each transition of the data strobe signal occurring after the first memory control signal is received comprises storing data in the memory device responsive to two transition of the data strobe signal occurring immediately after the first memory control signal is received.
18. The method of claim 15 wherein the act of discarding all of the saved data except for the data saved responsive to a predetermined number of transitions of the data strobe signal received prior to the first memory control signal comprises discarding all of the saved data except for the data saved responsive to two transitions of the data strobe signal received prior to the first memory control signal.