IP Library Granted Patent US 7,364,964
Granted Patent B2
US 7,364,964 · App. 11/133,267 · Granted Apr 29, 2008

Method of fabricating an interconnection layer above a ferroelectric capacitor

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,364,964
App. No.
11/133,267
Granted
Apr 29, 2008
Kind
B2
Abstract

A highly reliable semiconductor device having a ferroelectric capacitor structure by sufficiently preventing the H 2 attack without damaging the function of an interlayer insulating film covering interconnections and the like to obtain a high capacitor performance. The position of a semiconductor substrate mounted on and secured to a substrate support plate in an HDP-CVD system is adjusted in the vertical direction, whereby a second HDP-CVD oxide film is deposited so that voids are formed between aluminum interconnections at lower positions than the height of the aluminum interconnections.

Claims (26)

1. A method of fabricating a semiconductor device, comprising the steps of:

forming a capacitor structure above a substrate, the capacitor structure having a dielectric film comprising a ferroelectric material and being sandwiched between a bottom electrode and a top electrode;

forming an interconnection layer having a plurality of interconnections above the capacitor structure so as to connect at least a part of the interconnection layer with the capacitor structure; and

forming an upper interlayer insulating film comprising a high density plasma dielectric material so as to cover the interconnection layer

wherein the formation of the upper interlayer insulating film is controlled so that voids are formed between the interconnections disposed adjacently to each other at lower positions than the positions of the interconnections.

2. The method of fabricating a semiconductor device according to claim 1 , wherein

the upper interlayer insulating film is formed while controlling the formation of the voids by means of:

using a high density plasma CVD system that enables a substrate support plate on which the semiconductor substrate is mounted on and secured to move freely in the vertical direction in a chamber;

utilizing a fact that the density of a high density plasma dielectric material to be deposited becomes higher as the semiconductor substrate positions more upward in the chamber; and

adjusting the position of the semiconductor substrate mounted on and secured to the substrate support plate in the vertical direction in the chamber.

3. The method of fabricating a semiconductor device according to claim 1 , wherein

the upper interlayer insulating film is formed by sequentially stacking a first high density plasma dielectric film deposited by using a high density plasma CVD method with a low bias or un-bias, and a second high density plasma dielectric film deposited by using a high density plasma CVD method with a bias higher than the low bias.

4. The method of fabricating a semiconductor device according to claim 1 , further comprising the step of forming a hydrogen diffusion preventing film between the interconnection layer and the upper interlayer insulating film.

5. The method of fabricating a semiconductor device according to claim 4 , wherein

the hydrogen diffusion preventing film is formed of a material selected from the group consisting of aluminum oxide, aluminum nitride, tantalum oxide, tantalum nitride, titanium oxide, and zirconium oxide.

6. The method of fabricating a semiconductor device according to claim 1 , further comprising the step of forming a lower interlayer insulating film comprising a high density plasma dielectric material so as to cover the capacitor structure.

7. The method of fabricating a semiconductor device according to claim 6 , wherein

the lower interlayer insulating film is formed by sequentially stacking a first high density plasma dielectric film deposited by using a high density plasma CVD method with a low bias or un-bias, and a second high density plasma dielectric film deposited by using a high density plasma CVD method with a bias higher than the low bias.

8. The method of fabricating a semiconductor device according to claim 6 , further comprising the step of forming a hydrogen diffusion preventing film between the capacitor structure and the lower interlayer insulating film.

9. The method of fabricating a semiconductor device according to claim 6 , wherein

the lower interlayer insulating film is formed at a temperature in the range of 175° C. to 400° C.

10. The method of fabricating a semiconductor device according to claim 6 , further comprising the step of performing a plasma treatment on the lower interlayer insulating film by using N 2 or N 2 O gas at a temperature in the range of 200° C. to 450° C. after the lower interlayer insulating film has been formed.

11. The method of fabricating a semiconductor device according to claim 1 , wherein

the dielectric film is formed of PZT or SBT.

12. The method of fabricating a semiconductor device according to claim 1 , wherein

the upper interlayer insulating film is formed at a temperature in the range of 175° C. to 400° C.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR MEMORY SOLUTION LIMITED
Reel/Frame 053195/0249 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 20, 2005
From: IZUMI, KAZUTOSHI
To: FUJITSU LIMITED
Reel/Frame 016588/0349 →
Priority Claims (1)
JP 2004-351906 · Dec 3, 2004 · national
Continuity (1)
Related Publication 20060121685A1 · Jun 8, 2006