Methods for increasing photo alignment margins
Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.
1. A method for forming an integrated circuit, comprising:
forming a first pattern of mask lines over a substrate by performing pitch multiplication, wherein performing pitch multiplication comprises:
providing a plurality of mandrels over a substrate;
blanket depositing a layer of spacer material over the mandrels; and
anisotropically etching the spacer material to form spacers on sidewalls of the mandrels, wherein the spacers constitute the mask lines,
wherein portions of the lines extend in spaced, generally parallel relation to one another between first and second spaced planes extending perpendicular to the lines and other portions of the lines extend between third and fourth spaced planes extending perpendicular to the lines, wherein the portions of the lines are at an angle relative to the other portions of the lines; and
separately forming a second pattern over the substrate without pitch multiplication, wherein material defining the second pattern contacts at least some of the mask lines.
2. The method of claim 1 , wherein a distance separating the other portions of the lines is about 1.5 times or more greater than a distance separating the portions of the lines.
3. The method of claim 1 , further comprising transferring the first and second patterns to a hard mask layer.
4. The method of claim 3 , further comprising etching a substrate through the hard mask layer.
5. The method of claim 1 , wherein separately forming the second pattern comprises:
depositing a protective layer around the mask lines;
depositing a photoresist layer over the protective layer; and
forming a photoresist pattern in the photoresist layer.
6. The method of claim 5 , wherein separately forming the second pattern further comprises transferring the photoresist pattern to the protective layer to form the second pattern in the protective layer.
7. The method of claim 5 , wherein the protective layer is a bottom anti-reflective coating.
8. The method of claim 1 , wherein providing the plurality of mandrels comprises:
photolithographically forming a plurality of lines in a photoresist layer; and
transferring a pattern defined by the lines to an underlying layer of mandrel material to form the plurality of mandrels.
9. The method of claim 8 wherein the mandrel material comprises amorphous carbon.
10. The method of claim 1 , wherein forming the first pattern of mask lines further comprises selectively removing the mandrels relative to the spacers after anisotropically etching the spacer material.
11. The method of claim 1 , further comprising forming a protective mask over the mask lines.
12. The method of claim 11 , wherein forming the protective mask leaves ends of the mask lines unprotected by the mask.
13. The method of claim 12 , further comprising selectively removing the unprotected ends of the mask lines.
14. A method for forming an integrated circuit, comprising:
forming a first mask pattern, wherein forming the first mask pattern comprises:
providing a plurality of mandrels over a substrate;
blanket depositing a layer of spacer material on the mandrels; and
anisotropically etching the spacer material to form spacers on sidewalls of the mandrels, wherein first lengths of the spacers extend in spaced, generally parallel relation to one another and second lengths of the spacers extend at an angle of about 30-90° relative to the first lengths; and
subsequently forming a second mask pattern over the substrate, wherein material defining the second pattern contacts at least some of the spacers.
15. The method of claim 14 , further comprising transferring the first and the second patterns to the substrate, wherein transferring the first lengths of the first pattern to the substrate defines interconnects in an array region of a partially fabricated integrated circuit.
16. The method of claim 15 , wherein a pitch of the interconnects is about 100 nm or less.
17. The method of claim 15 , wherein the interconnects each have a width of about 50 nm and an edge roughness less than about 5 nm rms.
18. The method of claim 15 , wherein transferring the second lengths of the first pattern to the substrate defines interconnects in a periphery region of a partially fabricated integrated circuit.
19. The method of claim 15 , wherein transferring the second pattern to the substrate defines landing pads in a periphery region of a partially fabricated integrated circuit.
20. The method of claim 19 , wherein a minimum dimension of the landing pads is about 0.30 μm.
21. The method of claim 20 , wherein a minimum distance between the landing pads and an interconnect is about 0.20 μm or less.
22. The method of claim 21 , wherein a minimum distance between landing pads is about 0.40 μm or less.
23. A method for forming an integrated circuit, comprising:
providing a plurality of mandrels over a substrate;
providing spacers on sidewalls of the mandrels, wherein first lengths of the spacers extend in spaced, generally parallel relation to one another and second lengths of the spacers extend at an angle of about 30-90° relative to the first lengths;
selectively removing the mandrels to leave a mask pattern formed by the spacers;
subsequently forming a second mask pattern over the substrate, wherein material defining the second pattern contacts at least some of the second lengths of the spacers; and
transferring the mask pattern and the second mask pattern to the substrate.
24. The method of claim 23 , wherein material defining the second pattern contacts the spacers in a region corresponding to a periphery region of the integrated circuit and wherein the first lengths extend over an other region corresponding to an array region of the integrated circuit.
25. The method of claim 23 , wherein the integrated circuit is a memory device.