IP Library Granted Patent US 7,371,674
Granted Patent B2
US 7,371,674 · App. 11/315,532 · Granted May 13, 2008

Nanostructure-based package interconnect

Assignee: Intel Corporation
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Quick Facts
Patent No.
US 7,371,674
App. No.
11/315,532
Granted
May 13, 2008
Kind
B2
Abstract

An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic nano-wires extending from the nano-sized openings. The die is attached to a substrate via the nanostructure bump.

Claims (32)

1. A method comprising:

forming a nanostructure bump on a die, the nanostructure bump having a template defining nano-sized openings and metallic nano-wires grown from the nano-sized openings; and

attaching the die to a substrate via the nanostructure bump.

2. The method of claim 1 wherein forming the nanostructure bump comprises:

depositing an aluminum layer on the die;

patterning the aluminum layer;

anodizing the patterned aluminum layer to form an anodic aluminum oxide (AAO) template having the nano-sized openings being an ordered array of pores;

depositing a metal to form the metallic nano-wires into the pores; and

etching the AAO template.

3. The method of claim 2 wherein anodizing comprises:

controlling thickness of the AAO template.

4. The method of claim 2 wherein etching comprises:

controlling thickness of the AAO template.

5. The method of claim 1 wherein forming the nanostructure bump comprises:

spin coating the die with a polycarbonate film;

etching the polycarbonate film using an ion beam to create the nano-sized openings being holes, the etched polycarbonate film forming a polycarbonate template;

depositing a metal to form the metallic nano-wires in the holes; and

etching away at least a surface layer of the polycarbonate template in an organic solvent.

6. The method of claim 5 wherein spin coating the die comprises:

controlling thickness of the polycarbonate template.

7. A method comprising:

forming a nanostructure bump on a die, the nanostructure bump having a template defining nano-sized openings and metallic nano-wires grown from the nano-sized openings; and

attaching the die to a substrate via the nanostructure bump;

wherein attaching the die to the substrate comprises:

depositing solder paste on substrate pads on the substrate; and

reflowing the nanostructure bump to form joints with the solder paste.

8. A method comprising:

forming a nanostructure bump on a die, the nanostructure bump having a template defining nano-sized openings and metallic nano-wires grown from the nano-sized openings; and

attaching the die to a substrate via the nanostructure bump;

wherein attaching the die to the substrate comprises: thermo-sonically bonding the nanostructure bump with substrate pads on the substrate.

9. The method of claim 8 wherein attaching the die to the substrate further comprises:

forming a metal layer on the substrate pads having same type as a metal of the nano-wires before thermo-sonically bonding the nanostructure bump.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2005
From: SUH, DAEWOONG; RARAVIKAR, NACHIKET R.
To: INTEL CORPORATION
Reel/Frame 017407/0671 →
Continuity (1)
Related Publication 20070148949A1 · Jun 28, 2007