Scalable high density non-volatile memory cells in a contactless memory array
A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell includes a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack includes a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.
1. A non-volatile memory device comprising:
a plurality of trenches formed in a substrate, each pair of trenches defining a mesa;
a plurality of diffusion areas formed in the substrate, a mesa diffusion area formed in each mesa top and a trench diffusion area formed under each trench; and
a vertical non-volatile memory cell formed on each sidewall of the trench, each memory cell comprising a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks wherein each non-volatile gate insulator stack comprises a tunnel insulator layer formed on the trench sidewall and adjacent to the trench diffusion area, a deep trapping layer formed over the tunnel insulator, and a charge blocking layer formed over the deep trapping layer.
2. The device of claim 1 wherein each mesa diffusion area is linked to adjacent trench diffusion areas by vertical channel regions in which a vertical channel forms during operation of the adjacent vertical non-volatile memory cell.
3. The device of claim 1 and further including self-aligned local interconnect areas formed over each mesa diffusion area.
4. The device of claim 1 wherein each non-volatile gate insulator stack further comprises:
an injection silicon rich nitride layer formed between the deep trapping layer and the charge blocking layer.
5. The device of claim 1 wherein the fixed threshold element comprises a polysilicon control gate over an oxide layer.
6. The device of claim 1 wherein the trapping layer is a high dielectric constant material comprising embedded metal nano-dots.
7. The device of claim 1 wherein the charge blocking layer is comprised of one of: Al 2 O 3 , HfO 2 , ZrO 2 , or PrO 3.
8. The device of claim 1 wherein the deep trapping layer is one of silicon nano-crystals, a silicon rich insulator, or SiON.
9. The device of claim 6 wherein the embedded metal nano-dots comprise one of:
platinum (Pt), gold (Au), Cobalt (Co), or Tungsten (W).
10. A non-volatile memory device comprising:
a plurality of trenches formed in a substrate, each pair of trenches defining a mesa;
a plurality of diffusion areas formed in the substrate, a mesa diffusion area formed in each mesa top and a source diffusion area formed under each trench;
a buried diffusion line formed in each trench and coupled to the source diffusion area; and
a pair of non-volatile memory cells formed vertically in each trench, each memory cell formed along a sidewall and comprising a control gate formed vertically over an oxide layer and located between a pair of vertical trapping layer insulator stacks.
11. The device of claim 10 wherein the substrate is a p-type substrate and the plurality of diffusion areas are n+.
12. The device of claim 10 wherein the substrate is an n-type substrate and the plurality of diffusion areas are p− conductivity areas.
13. The device of claim 10 wherein the trapping layer is comprised of SiON.
14. The device of claim 10 wherein the device is coupled in a NAND architecture.
15. The device of claim 10 wherein the diffusion areas serially link each memory cell of adjacent memory cells.
16. The device of claim 10 wherein the source line diffusion areas serially link each memory cell in each trench.
17. The device of claim 10 wherein the non-volatile memory device is part of a serial memory string that is part of a contact-less, non-volatile memory array.
18. A contact-less, non-volatile memory array comprising:
a plurality of trenches formed in a substrate, each pair of trenches defining a mesa;
a plurality of diffusion areas formed in the substrate, a mesa diffusion area formed in each mesa top and a source diffusion area formed under each trench;
a buried diffusion line formed in each trench and coupled to the source diffusion area; and
a pair of non-volatile memory cells formed vertically in each trench, each memory cell formed along a sidewall and comprising a control gate formed over an oxide layer and located between a pair of vertical trapping insulator stacks having a tunnel insulator layer, an SiON trapping layer, and a charge blocking layer.
19. The array of claim 18 wherein the tunnel insulator layer is comprised of an oxide material and the control gate is comprised of polysilicon.
20. The array of claim 18 wherein the vertical trapping insulator stacks further comprise an injector silicon rich nitride layer between the SiON trapping layer and the charge blocking layer comprising a high dielectric constant material.
21. An electronic system comprising:
a processor that generates memory signals; and
a flash memory device coupled to the processor and operating in response to the memory signals, the device having a memory array comprising:
a plurality of trenches formed in a substrate, each pair of trenches defining a mesa;
a plurality of diffusion areas formed in the substrate, a mesa diffusion area formed in each mesa top and a trench diffusion area formed under each trench; and
a vertical non-volatile memory cell formed on each sidewall of the trench, each memory cell comprising a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks wherein each non-volatile gate insulator stack comprises a tunnel insulator layer formed on the trench sidewall and adjacent to the trench diffusion area, a deep trapping layer formed over the tunnel insulator, and a charge blocking layer formed over the deep trapping layer.