Method for testing memory under worse-than-normal conditions
View Patent ↗A method for testing a memory with cell plates and bit-line plates comprises putting the memory in a test mode, applying a test pattern to the memory, then providing a first voltage higher than Vdd/2 to the cell plate when writing a ‘1’ to a predetermined cell, providing a second voltage lower than Vdd/2 to the cell plate when writing a ‘0’ to a predetermined cell, wherein the first and second voltages are applied to emulate weak charge storage in the memory cell, similarly, providing a third voltage higher than Vdd/2 to the bit-line plate when expecting to read a ‘1’ from a predetermined cell, and providing a fourth voltage lower than Vdd/2 to the bit-line plate when expecting to read a ‘0’ from a predetermined cell, wherein the third and fourth voltages are applied to emulate charge decay in the memory cell.
1. A method for testing at least one memory with a plurality of charge storing cells coupled to a plurality of bit-lines and one or more cell plates for biasing the cells and one or more bit-line plates for biasing the bit-lines, the method comprising:
putting the memory in a test mode;
applying a test pattern to the memory;
providing a first voltage higher than one half of a positive supply voltage (Vdd) to the cell plate when writing a ‘1’ to a predetermined cell; and
providing a second voltage lower than one half of the Vdd to the cell plate when writing a ‘0’ to a predetermined cell,
wherein the first and second voltages are applied to emulate weak charge storage in the memory cell.
2. The method of claim 1 , wherein the applying further comprises applying a March test pattern.
3. The method of claim 1 , wherein the providing the first or second voltage further comprises providing the cell plate with a certain voltage level during an entire period when writing all ‘1s’ or all ‘0s’ to all the predetermined cells.
4. The method of claim 1 further comprising:
providing a third voltage higher than one half of the Vdd to the bit-line plate when expecting to read a ‘1’ from a predetermined cell; and
providing a fourth voltage lower than one half of the Vdd to the bit-line plate when expecting to read a ‘0’ from a predetermined cell,
wherein the third and fourth voltages are applied to emulate charge decay in the memory cell.
5. The method of claim 4 , wherein the providing the third or fourth voltage further comprises providing the bit-line plate with a certain voltage level during an entire period when expecting to read all ‘1s’ or all ‘0s’ from all the predetermined cells.
6. The method of claim 1 , wherein the memory is a dynamic random access memory (DRAM).
7. A method for testing at least one memory with a plurality of charge storing cells coupled to a plurality of bit-lines and one or more cell plate for biasing the cells and one or more bit-line plate for biasing the bit-lines, the method comprising:
putting the memory in a test mode;
applying a test pattern to the memory;
providing a first voltage higher than one half of a positive supply voltage (Vdd) to the bit-line plate when expecting to read a ‘1’ from a predetermined cell; and
providing a second voltage lower than one half of the Vdd to the bit-line plate when expecting to read a ‘0’ from a predetermined cell,
wherein the first and second voltages are applied to emulate charge decay in the memory cell.
8. The method of claim 7 , wherein the applying further comprises applying a March test pattern.
9. The method of claim 7 , wherein the providing the first or second voltage further comprises providing the bit-line plate with a certain voltage level during an entire period when expecting to read all ‘1s’ or all ‘0s’ from all the predetermined cells.
10. The method of claim 7 further comprising:
providing a third voltage higher than one half of the Vdd to the cell plate when writing a ‘1’ to a predetermined cell; and
providing a fourth voltage lower than one half of the Vdd to the cell plate when writing a ‘0’ to a predetermined cell,
wherein the third and fourth voltages are applied to emulate charge decay in the memory cell.
11. The method of claim 10 , wherein the providing the third or fourth voltage further comprises providing the cell plate with a certain voltage level during an entire period when writing all ‘1s’ or all ‘0s’ to all the predetermined cells.
12. The method of claim 7 , wherein the memory is a dynamic random access memory (DRAM).
13. A method for testing at least one memory with a plurality of charge storing cells coupled to a plurality of bit-lines and one or more cell plates for biasing the cells and one or more bit-line plate for biasing the bit-lines, the method comprising:
putting the memory in a test mode;
applying a test pattern to the memory;
providing a first voltage higher than one half of a positive supply voltage (Vdd) to the cell plate when writing a ‘1’ to a predetermined cell;
providing a second voltage lower than one half of the Vdd to the cell plate when writing a ‘0’ to a predetermined cell;
providing a third voltage higher than one half of the Vdd to the bit-line plate when expecting to read a ‘1’ from a predetermined cell; and
providing a fourth voltage lower than one half of the Vdd to the bit-line plate when expecting to read a ‘0’ from a predetermined cell,
wherein the first and second voltages are applied to emulate weak charge storage in the memory cell, and the third and fourth voltages are applied to emulate charge decay in the memory cell.
14. The method of claim 13 , wherein the applying further comprises applying a March test pattern.
15. The method of claim 13 , wherein the providing the first or second voltage further comprises providing the cell plate with a certain voltage level during an entire period when writing all ‘1s’ or all ‘0s’ to all the predetermined cells.
16. The method of claim 13 , wherein the providing the third or fourth voltage further comprises providing the bit-line plate with a certain voltage level during an entire period when expecting to read all ‘1s’ or all ‘0s’ from all the predetermined cells.
17. The method of claim 13 , wherein the memory is a dynamic random access memory (DRAM).