Methods of forming hybrid fin field-effect transistor structures
Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide.
1. A method for forming a structure, the method comprising:
providing a substrate having an insulator layer disposed thereon, and a bilayer disposed in contact with the insulator layer, the bilayer including a second strained semiconductor layer disposed over a first strained semiconductor layer; and
thereafter forming a fin field-effect transistor on the substrate by:
patterning the bilayer to define a source region, a drain region, and at least one fin disposed between the source and the drain regions,
forming a gate dielectric layer at least a portion of which is disposed over the fin, and
forming a gate over the gate dielectric layer portion disposed over the fin,
wherein a strain of the first strained semiconductor layer is different from a strain of the second strained semiconductor layer.
2. The method of claim 1 , wherein the bilayer comprises at least one of a group II, a group III, a group IV, a group V, or a group VI element.
3. The method of claim 1 , wherein the first strained semiconductor layer is tensilely strained.
4. The method of claim 3 , wherein the second strained semiconductor layer is compressively strained.
5. The method of claim 1 , wherein patterning the bilayer comprises removing a portion of the first strained semiconductor layer and a portion of the second strained semiconductor layer.
6. The method of claim 1 , wherein the bilayer comprises a second semiconductor material disposed over a first semiconductor material, and the first semiconductor material is different from the second semiconductor material.
7. The method of claim 1 , wherein a thickness of the first strained semiconductor layer is greater than a thickness of the second strained semiconductor layer such that the sidewalls of the fin are primarily defined by the first strained semiconductor layer.
8. The method of claim 1 , wherein the second strained semiconductor layer is tensilely strained.
9. The method of claim 6 , wherein the first strained semiconductor layer is compressively strained.