Low temperature CVD process with selected stress of the CVD layer on CMOS devices

1. A method of forming coatings on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out the following deposition steps:

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a region of a reentrant conduit external of the chamber and forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece below a threshold photoresist removal temperature;

setting said RF plasma source power at a level at which the coating is deposited non-conformally; and

setting said RF bias voltage at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.

2. The method of claim 1 wherein said first stress is a compressive stress and said second stress is a tensile stress.

3. The method of claim 1 further comprising:

following removal of photoresist from the workpiece, coating the workpiece with a passivation layer having zero stress and high conformality by setting said RF plasma bias voltage for low or at least nearly zero stress and setting said RF plasma source power for maximum conformality while continuing to generate said RF torroidal plasma current.

4. The reactor of claim 1 wherein said first frequency is about an order of magnitude greater than said second frequency.

5. The reactor of claim 1 wherein said first frequency is an HF frequency and said second frequency is an LF frequency.

6. The reactor of claim 1 wherein said first frequency is on the order of ten or tens of MHz and said second frequency is on the order of one or a few MHz.

7. The process of claim 1 wherein said semiconductor element comprises silicon.

8. A method of forming device enhancing coatings on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

placing a first photoresist mask over one of the sets of N-channel and P-channel devices while leaving the other set exposed,

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a portion of an external conduit forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece under a threshold temperature below which the photoresist mask is not destroyed;

setting said RF plasma source power at a level at which the coating is deposited with a first value of conformality lying in a range between maximum conformality and maximum non-conformality;

setting said RF bias voltage at a level at which the coating is deposited with a first stress if the one set consists of the P-channel devices and with a second stress if the one set consists of N-channel devices;

removing the first photoresist mask and placing a second photoresist mask over the other of the sets of N-channel and P-channel devices,

setting said RF plasma source power at a level at which the coating is deposited with a second value of conformality lying in a the range between minimum conformality and maximum non-conformality; and

setting said RF bias voltage at a level at which the coating is deposited with a first stress if the other set consists of the P-channel devices and with a second stress if the other set consists of N-channel devices.

9. The method of claim 8 wherein said first value of conformality corresponds to a non-conformal coating, said second value of conformality corresponds to a conformal coating, said first stress is a compressive stress and said second stress is a tensile stress.

10. The method of claim 8 further comprising:

removing said second photoresist mask;

coating the workpiece with a passivation layer having zero stress and high conformality by setting said RF plasma bias voltage for zero stress and setting said RF plasma source power for maximum conformality while continuing to generate said RF torroidal plasma current.

11. The reactor of claim 8 wherein said first frequency is about an order of magnitude greater than said second frequency.

12. The reactor of claim 8 wherein said first frequency is an HF frequency and said second frequency is an LF frequency.

13. The reactor of claim 8 wherein said first frequency is on the order of ten or tens of MHz and said second frequency is on the order of one or a few MHz.

14. The process of claim 8 wherein said semiconductor element comprises silicon.

15. A method of forming a device enhancing coating on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a portion of an external conduit forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece under a threshold temperature below which the photoresist mask is not destroyed;

setting said RF bias voltage at a level lying within a range including zero volts at which the coating is deposited with one of: (a) compressive stress, (b) tensile stress;

placing a photoresist mask over one of (a) the N-channel devices, (b) the P-channel devices, respectively,

ion implanting into the exposed portion of the coating at least one of hydrogen and helium with sufficient bias voltage and implant dose to transform the stress in said exposed portion from one of (a) compressive, (b) tensile, to the other.

16. The process of claim 15 wherein said semiconductor element comprises silicon.