IP Library › Granted Patent US 7,393,770
Granted Patent B2
US 7,393,770 · App. 11/133,085 · Granted Jul 1, 2008

Backside method for fabricating semiconductor components with conductive interconnects

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,393,770
App. No.
11/133,085
Granted
Jul 1, 2008
Kind
B2
Abstract

A backside method for fabricating a semiconductor component with a conductive interconnect includes the step of providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side. The method also includes the steps of forming a substrate opening from the backside to the substrate contact, and then bonding the conductive interconnect to an inner surface of the substrate contact. A system for performing the method includes the semiconductor substrate, a thinning system for thinning the semiconductor substrate, an etching system for forming the substrate opening, and a bonding system for bonding the conductive interconnect to the substrate contact. The semiconductor component can be used to form module components, underfilled components, stacked components, and image sensor semiconductor components.

Claims (39)

1. A method for fabricating a semiconductor component comprising:

providing a semiconductor substrate having a circuit side, a backside, and a substrate contact on the circuit side having an inner surface;

forming an opening from the backside to the inner surface of the substrate contact; and

forming a conductive interconnect comprising a wire from the backside through the opening to the substrate contact having a bonded connection with the inner surface of the substrate contact using a bonding capillary placed in the opening and operated to form the bonded connection; and forming a dielectric encapsulant on the backside encapsulating at least a portion of the conductive interconnect.

2. The method of claim 1 further comprising thinning the substrate from the backside prior to the forming the conductive interconnect step.

3. The method of claim 1 wherein the forming the conductive interconnect step further comprises forming a second bonded connection on a second substrate contact on the backside of the substrate using the bonding capillary.

4. The method of claim 1 further comprising bonding the conductive interconnect to a second substrate contact on the backside of the substrate.

5. The method of claim 1 further comprising stacking a second substrate on the substrate having a second substrate contact bonded to the conductive interconnect.

6. The method of claim 1 further comprising forming a first bump on the inner surface of the substrate contact and wherein the forming the conductive interconnect step bonds the conductive interconnect to the first bump.

7. The method of claim 1 wherein the conductive interconnect projects from the backside with a selected length.

8. The method of claim 1 wherein the substrate comprises a plurality of substrate contacts and the opening encircles the substrate contacts.

9. A method for fabricating a semiconductor component comprising:

providing a semiconductor substrate having a circuit side, a backside, a first contact on the circuit side having an inner surface, and a second contact on the backside;

forming a substrate opening in the semiconductor substrate from the backside to the inner surface of the first contact; and

forming a conductive interconnect from the back side on the inner surface of the first contact and on the second contact using a bonding capillary, the conductive interconnect comprising a wire having a first bonded connection on the inner surface and a second bonded connection on the second contact and forming a dielectric encapsulant on the backside encapsulating at least a portion of the conductive interconnect.

10. The method of claim 9 further comprising forming a terminal contact on the backside in electrical communication with the second contact.

11. A method for fabricating a semiconductor component comprising:

providing a semiconductor substrate having a circuit side, a backside, a first contact on the circuit side having an inner surface, and a second contact on the backside;

forming a substrate opening in the semiconductor substrate from the backside to the inner surface of the first contact; and

forming a conductive interconnect from the back side on the inner surface of the first contact and on the second contact, the conductive interconnect comprising a wire having a first bonded connection on the inner surface and a second bonded connection on the second contact, the first bonded connection comprising a ball bond and the second bonded connection comprising a wedge bond; and forming a dielectric encapsulant on the backside encapsulating at least a portion of the conductive interconnect.

12. A method for fabricating a stacked semiconductor component comprising:

providing a first semiconductor component having a circuit side, a backside, a contact on the circuit side having an inner surface, and an opening extending from the circuit side to the backside;

forming a conductive interconnect on the first semiconductor component using a bonding capillary, the conductive interconnect comprising a wire in the opening having a bonded connection on the inner surface of the contact; and

bonding a second semiconductor component to the first semiconductor component by forming a second bonded connection between the conductive interconnect and a second substrate contact on the second semiconductor component; and forming a dielectric encapsulant on the backside encapsulating at least a portion of the conductive interconnect.

13. The method of claim 12 wherein the wire projects from the opening with a selected length and the second semiconductor component includes a plated opening configured to receive the wire.

14. The method of claim 12 wherein the first semiconductor component comprises a semiconductor die and the second semiconductor component comprises a support substrate.

15. The method of claim 12 wherein the first semiconductor component and the second semiconductor component comprise semiconductor dice.

16. The method of claim 12 wherein the bonded connection comprises a wire bond.

17. The method of claim 12 further comprising forming an underfill layer between the first semiconductor component and the second semiconductor component substantially encapsulating the conductive interconnect.

18. The method of claim 12 wherein the first semiconductor component comprises an image sensor semiconductor component.

19. The method of claim 12 wherein the first semiconductor component comprises an image sensor semiconductor component and the second semiconductor component comprises a semiconductor die.

20. A method for fabricating a semiconductor component comprising:

providing a bonding capillary configured to wire bond a wire;

providing a semiconductor substrate having a circuit side, a backside, an integrated circuit, and a substrate contact on the circuit side in electrical communication with the integrated circuit having an inner surface;

forming an opening in the semiconductor substrate from the backside to the inner surface of the substrate contact; and

forming a conductive interconnect in the opening using the bonding capillary, the conductive interconnect comprising the wire and a bonded connection between the wire and the inner surface; and forming a dielectric encapsulant on the backside encapsulating at least a portion of the conductive interconnect.

21. The method of claim 20 further comprising bonding a second semiconductor substrate having a second conductive interconnect bonded to the conductive interconnect.

22. The method of claim 21 further comprising forming a dielectric layer between the first semiconductor component and the second semiconductor component.

23. The method of claim 20 further comprising forming a conductor on the backside in electrical communication with the wire, and a terminal contact on the backside in electrical communication with the conductor.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 16, 2006
From: WOOD, ALAN G.; HIATT, WILLIAM M.; HEMBREE, DAVID R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 017568/0719 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2005
From: WOOD, ALAN G.; HIATT, WILLIAM M.; HENBREE, DAVID R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 016591/0415 →
RE-RECORD TO CORRECT A DOCUMENT PREVIOUSLY RECORDED AT REEL 015526, FRAME 0803. (ASSIGNMENT OF ASSIGNOR'S INTEREST) Recorded May 19, 2005
From: WOOD, ALAN G.; HIATT, WILLIAM M.; HENBREE, DAVID R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 017120/0446 →
Continuity (1)
Related Publication 20060261446A1 · Nov 23, 2006