Protective coating for planarization
Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane.
1. A method of planarizing a structure in a partially fabricated integrated circuit, the method comprising:
providing elevated, pitch doubled features in a first region, the elevated features having spaces among them;
depositing a filler layer over the first region and an adjacent second region;
providing a protective layer over the filler layer, the protective layer being thinner over the first region compared to the second region; and
planarizing the filler layer after providing the protective layer.
2. The method of claim 1 , wherein the elevated features are lines in a memory array.
3. The method of claim 1 , wherein the filler layer fills the spaces among the features.
4. The method of claim 3 , wherein planarizing comprises exposing tops of the features and leaving the filler layer between the features and not over the features.
5. The method of claim 1 , wherein planarizing comprises chemical vapor deposition.
6. The method of claim 1 , wherein planarizing comprises dry etching.
7. The method of claim 1 , wherein the protective layer prevents removal of the filler layer in the second region while planarizing the filler layer in the first region.
8. The method of claim 1 , wherein planarizing comprises removing the protective layer in the first region before removing the protective layer in the second region.
9. A method of forming an array for an integrated circuit comprising:
forming pitch-multiplied features separated by spaces in a first region;
introducing a filler layer that fills the spaces and covers the pitch-multiplied features in the first region and covers the surface of a second region;
coating the filler layer with a protective layer in both the first and second regions;
removing a portion of the protective layer in the first region;
allowing a portion of the protective layer to remain covering the filler layer in the second region;
removing portions of filler layer through planarization of the first region while the filler layer is still protected by the protective layer in the second region;
removing the protective layer and planarizing the first and second regions to the same plane; and
forming a mask over at least one of the first and second regions.
10. The method of claim 9 , further comprising planarizing the first region down to the top of the pitch-multiplied features so that the filler material forms discontinuous portions in between the pitch-multiplied features.
11. The method of claim 9 , wherein the mask is pitch multiplied.
12. The method of claim 9 , wherein the pitch multiplied features are spacers.
13. The method of claim 9 , wherein the protective layer has poor step coverage.
14. The method of claim 9 , wherein the protective layer is a definable layer.
15. The method of claim 9 , wherein the protective layer is photoresist.
16. The method of claim 9 , wherein the filler layer is amorphous carbon.
17. The method of claim 9 , wherein the filler layer in the first region has a surface with hills and valleys that are filled an planarized by the protective layer.
18. The method of claim 9 , wherein the filler layer has approximately the same maximum thickness over the pitch-multiplied features as it does in the second region.
19. The method of claim 9 , wherein the protective layer is thinner in the first region than it is in the second region.
20. The method of claim 9 , wherein the protective layer has a top surface that is approximately on the same plane in both the first and second regions after being deposited over the filler layer.
21. The method of claim 9 , wherein the protective material has a top surface that generally is higher in the first region than in the second region.
22. The method of claim 9 , wherein the protective layer is spun on.
23. A method of manufacturing computer memory comprising:
forming separated features in a memory array region;
depositing a filler layer around and over the features in the memory array region and in a peripheral region such that the surface of the filler layer is non-planar;
forming a protective layer over the filler layer in both the memory array region and the peripheral region;
exposing the filler layer under the protective layer in the array region before exposing the filler layer under the protective layer in the peripheral region; and
reducing the height of the features and filler layer in the memory array region to approximately the same height as the filler layer in the peripheral region.
24. The method of claim 23 , wherein the separated features comprise masking features.
25. The method of claim 23 , wherein the surface of the filler layer is less smooth than the surface of the peripheral region prior to formation of the protective layer.
26. The method of claim 23 , wherein the separated features comprise spacers.
27. The method of claim 23 , wherein the separated features comprise lines of sacrificial material.
28. The method of claim 27 , wherein the lines of sacrificial material are pitch reduced.
29. The method of claim 23 , wherein the peripheral region is a logic region.
30. The method of claim 23 , wherein an upper surface of the peripheral region is lower than an upper surface of the memory array region prior to depositing the filler layer.
31. The method of claim 23 , wherein forming a protective layer comprises applying a spin-on coat of photoresist.
32. The method of claim 23 , wherein the protective layer is generally thinner in the memory array region when it is formed than it is in the peripheral region.
33. The method of claim 23 , wherein exposing the filler layer under the protective layer in the array region before exposing the filler layer in the periphery region is accomplished by a selective etch.
34. The method of claim 23 , wherein exposing the filler layer under the protective layer in the array region before exposing the filler layer in the periphery region is accomplished by a timed etch.
35. The method of claim 23 , wherein the protective layer in the memory array region is removed before the protective layer is removed in the peripheral region.
36. The method of claim 23 , wherein reducing feature heights comprises a chemical mechanical planarization process.
37. The method of claim 23 , wherein reducing feature heights comprises a dry etch process.
38. The method of claim 23 , wherein exposing the filler layer comprises first exposing portions of the filler layer that are taller before exposing portions of the filler layer that are lower.
39. The method of claim 23 , wherein forming a protective layer comprises forming a protective layer that is thinner over taller portions of topography in the filler layer and thicker over shorter portions of the topography in the filler layer.