Reducing floating gate to floating gate coupling effect

1. A method for operating non-volatile memory, comprising:

erasing a set of non-volatile storage elements by intentionally moving threshold voltages for said non-volatile storage elements to a first range of threshold voltages, said first range is not a valid data range;

compressing said threshold voltages and moving said threshold voltages from said first range to a second range of threshold voltages; and

performing a multi-pass programming process that programs at least a subset of said non-volatile storage elements from said second range to one or more of additional ranges that are valid data ranges.

2. A method according to claim 1 , wherein:

said multi-pass programming process includes a first pass and a second pass;

said first pass includes programming at least some of said non-volatile storage elements from said second range to a third range of threshold voltages; and

said second pass includes programming a first subset of non-volatile storage elements from said second range of threshold voltages to a fourth range of threshold voltages, programming a second subset of non-volatile storage elements from said second range of threshold voltages to a fifth range of threshold voltages, programming a third subset of non-volatile storage elements from said third range of threshold voltages to a sixth range of threshold voltages, and programming a fourth subset of non-volatile storage elements from said third range of threshold voltages to a seventh range of threshold voltages.

3. A method according to claim 2 , wherein:

said multi-pass programming process includes a third pass; and

said third pass includes:

programming a fifth subset of non-volatile storage elements from said fourth range of threshold voltages to an eighth range of threshold voltages,

programming a sixth subset of non-volatile storage elements from said fourth range of threshold voltages to a ninth range of threshold voltages,

programming a seventh subset of non-volatile storage elements from said fifth range of threshold voltages to a tenth range of threshold voltages,

programming a eighth subset of non-volatile storage elements from said fifth range of threshold voltages to a eleventh range of threshold voltages.

programming a ninth subset of non-volatile storage elements from said sixth range of threshold voltages to an twelfth range of threshold voltages,

programming a tenth subset of non-volatile storage elements from said sixth range of threshold voltages to a thirteenth range of threshold voltages,

programming a eleventh subset of non-volatile storage elements from said seventh range of threshold voltages to a fourteenth range of threshold voltages, and

programming a twelfth subset of non-volatile storage elements from said seventh range of threshold voltages to a fifteenth range of threshold voltages.

4. A method according to claim 3 , wherein:

each of said non-volatile storage elements stores data in multiple pages; and

said multi-pass programming process includes writing to a particular non-volatile storage element with respect to a particular page subsequent to writing to adjacent non-volatile storage elements for previous pages.

5. A method according to claim 2 , wherein:

said fourth range of threshold voltages is a tightened version of said second range of threshold voltages; and

said sixth range of threshold voltages is a tightened version of said third range of threshold voltages.

6. A method according to claim 2 , wherein:

each of said non-volatile storage elements stores data in multiple pages; and

said multi-pass programming process includes writing to a particular non-volatile storage element with respect to a particular page subsequent to writing to an adjacent non-volatile storage elements for a previous page.

7. A method according to claim 1 , wherein:

said multi-pass programming process includes a first pass and a second pass;

said first pass includes programming at least some of said non-volatile storage elements from said second range to a third range of threshold voltages; and

said second pass includes programming a first subset of non-volatile storage elements from said second range of threshold voltages to a fourth range of threshold voltages and programming another subset of non-volatile storage elements from said third range of threshold voltages to another range of threshold voltages.

8. A method according to claim 1 , wherein:

each of said non-volatile storage elements stores data in multiple pages; and

said multi-pass programming process includes writing to a particular non-volatile storage element with respect to a particular page subsequent to writing to an adjacent non-volatile storage elements for a previous page.

9. A method according to claim 1 , wherein:

said first range of threshold voltages is below zero volts;

said additional ranges are above zero volts.

10. A method according to claim 1 , wherein:

said erasing includes removing charge from floating gates for said non-volatile storage elements; and

said compressing and moving includes adding charge to floating gates for said non-volatile storage elements.

11. A method according to claim 1 , wherein:

said non-volatile storage elements are multi-state NAND flash memory elements.

12. A method according to claim 1 , wherein:

said non-volatile storage elements are multi-state flash memory elements.

13. A method according to claim 1 , wherein said moving said threshold voltages from said first range to said second range of threshold voltages includes moving said threshold voltages from a first state of a plurality of non-overlapping states to a second state of the plurality of non-overlapping states.

14. A method for operating non-volatile storage, comprising:

erasing a plurality of non-volatile storage elements to an erased threshold voltage distribution, said erased threshold voltage distribution is not a valid data threshold voltage distribution; and

moving threshold voltages for said non-volatile storage elements from said erased threshold voltage distribution to a set of valid data threshold voltage distributions, said moving threshold voltages includes using a multi-pass programming process that programs at least a subset of said non-volatile storage elements from said erased threshold voltage distribution to said set of valid data threshold voltage distributions.

15. A method according to claim 14 , wherein:

said moving threshold voltages includes performing a first pass and a second pass;

said first pass includes programming at least some of said non-volatile storage elements from a first threshold voltage distribution to a second threshold voltage distribution; and

said second pass includes programming a first subset of non-volatile storage elements from said first threshold voltage distribution to a third threshold voltage distribution, programming a second subset of non-volatile storage elements from said first threshold voltage distribution to a fourth threshold voltage distribution, programming a third subset of non-volatile storage elements from said second threshold voltage distribution to a fifth threshold voltage distribution, and programming a fourth subset of non-volatile storage elements from said second threshold voltage distribution to a sixth threshold voltage distribution.

16. A method according to claim 15 , wherein:

each of said non-volatile storage elements stores data in multiple pages; and

said multi-pass programming process includes writing to a particular non-volatile storage element with respect to a particular page subsequent to writing to an adjacent non-volatile storage element for a previous page.

17. A method according to claim 14 , wherein:

said non-volatile storage elements are multi-state flash memory elements.

18. A method according to claim 14 , wherein:

said erased threshold voltage distribution is below zero volts; and

said valid data threshold voltage distributions are above zero volts.

19. A non-volatile memory system, comprising:

a plurality of non-volatile storage elements;

means for erasing said non-volatile storage elements by intentionally moving threshold voltages for said non-volatile storage elements to a first range of threshold voltages, said first range is not a valid data range;

means for compressing said threshold voltages and moving said threshold voltages from said first range to a second range of threshold voltages; and

means for performing a multi-pass programming process that programs at least a subset of said non-volatile storage elements from said second range to one or more of additional ranges that are valid data ranges.

20. A non-volatile memory system according to claim 19 , wherein said means for compressing said threshold voltages and moving said threshold voltages includes means for moving said threshold voltages from a first state of a plurality of non-overlapping states to a second state of the plurality of non-overlapping states.

21. A non-volatile memory system, comprising:

a plurality of non-volatile storage elements; and

one or more control circuits in communication with said non-volatile storage elements, said one or more control circuits erase said non-volatile storage elements by intentionally moving threshold voltages for said non-volatile storage elements to a first range of threshold voltages that is not associated with valid data, said one or more control circuits compress said threshold voltages and move said threshold voltages from said first range to a second range of threshold voltages, said one or more control circuits perform a multi-pass programming process that programs at least a subset of said non-volatile storage elements from said second range to one or more of additional ranges that are valid data ranges.

22. The non-volatile memory system according to claim 21 , wherein:

said multi-pass programming process includes said one or more control circuits performing a first pass and a second pass;

said first pass includes said one or more control circuits programming at least some of said non-volatile storage elements from said second range to a third range of threshold voltages; and

said second pass includes said one or more control circuits programming a first subset of non-volatile storage elements from said second range of threshold voltages to a fourth range of threshold voltages, programming a second subset of non-volatile storage elements from said second range of threshold voltages to a fifth range of threshold voltages, programming a third subset of non-volatile storage elements from said third range of threshold voltages to a sixth range of threshold voltages, and programming a fourth subset of non-volatile storage elements from said third range of threshold voltages to a seventh range of threshold voltages.

23. The non-volatile memory system according to claim 21 , wherein:

each of said non-volatile storage elements stores data in multiple pages; and

said multi-pass programming process includes said one or more control circuits writing to a particular non-volatile storage element with respect to a particular page subsequent to writing to an adjacent non-volatile storage element for a previous page.

24. The non-volatile memory system according to claim 21 , wherein:

said first range of threshold voltages is below zero volts;

said additional ranges are above zero volts.

25. The non-volatile memory system according to claim 21 , wherein:

said non-volatile storage elements are multi-state NAND flash memory elements.

26. The non-volatile memory system according to claim 21 , wherein:

said non-volatile storage elements are multi-state flash memory elements.

27. A non-volatile memory system according to claim 21 , wherein said first range of threshold voltages is a first state of a plurality of non-overlapping states and said second range of threshold voltages is a second state of the plurality of non-overlapping states.

28. A non-volatile memory system, comprising:

a plurality of non-volatile storage elements; and

one or more control circuits in communication with said non-volatile storage elements, said one or more control circuits erase said non-volatile storage elements to an erased threshold voltage distribution that is not associated with valid data, said one or more control circuits move threshold voltages for said non-volatile storage elements from said erased threshold voltage distribution to a set of valid data threshold voltage distributions, said moving threshold voltages includes said one or more control circuits using a multi-pass programming process that programs said non-volatile storage elements from said erased threshold voltage distribution to said set of valid data threshold voltage distributions.

29. A non-volatile memory system according to claim 28 , wherein:

said one or more control circuits move threshold voltages by performing a first pass and a second pass;

said first pass includes said one or more control circuits programming at least some of said non-volatile storage elements from a first threshold voltage distribution to a second threshold voltage distribution; and

said second pass includes said one or more control circuits programming a first subset of non-volatile storage elements from said first threshold voltage distribution to a third threshold voltage distribution, programming a second subset of non-volatile storage elements from said first threshold voltage distribution to a fourth threshold voltage distribution, programming a third subset of non-volatile storage elements from said second threshold voltage distribution to a fifth threshold voltage distribution, and programming a fourth subset of non-volatile storage elements from said second threshold voltage distribution to a sixth threshold voltage distribution.

30. A non-volatile memory system according to claim 28 , wherein:

each of said non-volatile storage elements stores data in multiple pages; and

said multi-pass programming process includes said one or more control circuits writing to a particular non-volatile storage element with respect to a particular page subsequent to writing to an adjacent non-volatile storage element for a previous page.

31. A non-volatile memory system according to claim 28 , wherein:

said non-volatile storage elements are multi-state flash memory elements.

32. A non-volatile memory system according to claim 28 , wherein:

said erased threshold voltage distribution is below zero volts; and

said valid data threshold voltage distributions are above zero volts.

33. A non-volatile memory system according to claim 28 , wherein the set includes at least two valid data threshold voltage distributions.