Method of forming through-silicon vias with stress buffer collars and resulting devices
A method of forming a via having a stress buffer collar, wherein the stress buffer collar can absorb stress resulting from a mismatch in the coefficients of thermal expansion of the surrounding materials. Other embodiments are described and claimed.
1. A method comprising:
forming a via in a substrate, the via having a sidewall and a bottom, the substrate comprised of a first material;
depositing a layer of a buffer material in the via such that the layer of the buffer material completely fills the via;
forming a hole in the buffer material, the hole extending to proximate the bottom of the via; and
depositing a second material to completely fill the second material in the hole in the buffer material within the via, wherein the buffer material is capable of absorbing stress due to a thermal expansion mismatch between the first and second materials wherein the first material comprises silicon and the second material comprises copper.
2. The method of claim 1 , wherein a coefficient of thermal expansion (CTE) of the buffer material is approximately equal to a CTE of copper.
3. The method of claim 1 , wherein a CTE of the buffer material is approximately equal to a mean of a CTE of silicon and a CTE of copper.
4. The method of claim 1 , wherein the buffer material comprises a relatively compliant material in comparison to silicon and copper.
5. The method of claim 1 , wherein the buffer material comprises a material selected from a group including silicones, acrylates, polyimides, benzocyclobutene (BCB), parylenes, fluorocarbons, polyolefins, polyesters, and epoxies.
6. The method of claim 1 , wherein the substrate comprises a silicon wafer, the silicon wafer having circuitry formed on a front side and an opposing back side, and wherein forming a via comprises forming a via from the wafer backside, the via extending to a conductor proximate the wafer front side.
7. The method of claim 1 , wherein the hole is formed using a process selected from a group consisting of laser ablation, etching, lithography, and milling.
8. The method of claim 1 , wherein the layer of buffer material is deposited using a spin-coating process.
9. The method of claim 1 , wherein the layer of buffer material is deposited using a chemical-vapor deposition (CVD) process.
10. The method of claim 1 , further comprising depositing at least one of an insulating layer and a passivation layer in the via prior to deposition of the buffer material.
11. The method of claim 10 , further comprising removing a portion of the at least one layer from a bottom of the via.
12. The method of claim 1 , further comprising depositing at least one of a seed layer and a barrier layer over the buffer material prior to deposition of the second material.
13. A method comprising:
forming a via in a substrate, the via having a sidewall and a bottom the substrate comprised of a first material having a first coefficient of thermal expansion (CTE);
depositing a second material in the via such that the second material completely fills the via, the second material having a second CTE;
forming a hole in the second material the hole extending to proximate the bottom of the via; and
depositing a third material to completely fill the third material in the hole in the second material within the via, the third material having a third CTE;
wherein the second CTE is in a range between the first CTE and the third CTE wherein the first material comprises silicon and the third material comprises copper.
14. The method of claim 13 , wherein the second CTE is approximately equal to the third CTE.
15. The method of claim 13 , wherein the second CTE is approximately equal to a mean of the first CTE and the third CTE.
16. The method of claim 13 , wherein second material comprises a material selected from a group including silicones, acrylates, polyimides, benzocyclobutene (BCB), parylenes, fluorocarbons, polyolefins, polyesters, and epoxies.
17. The method of claim 13 , wherein the second material comprises a relatively compliant material in comparison to first and third materials.
18. A method comprising:
forming a via in a substrate, the via having a sidewall and a bottom the substrate comprised of a first material;
depositing a layer of a buffer material in the via such that the layer of the buffer material completely fills the via;
forming a hole in the buffer material, the hole extending to proximate the bottom of the via; and
depositing a second material to completely fill the second material in the hole in the buffer material;
wherein the buffer material comprises a relatively compliant material in comparison to the first and second materials.
19. The method of claim 18 , wherein each of the first and second materials has a modulus of elasticity greater than approximately 40 GPa.
20. The method of claim 19 , wherein the buffer material has a modulus of elasticity less than approximately 10 GPa.
21. The method of claim 20 , wherein the buffer material has a modulus of elasticity greater than approximately 0.001 GPa.
22. The method of claim 18 , wherein the buffer material has a coefficient of thermal expansion (CTE) in a range between approximately a CTE of the first material and a CTE of the second material.