Dynamic random access memory trench capacitors
DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
1. A semiconductor structure comprising:
a trench capacitor, including:
a trench formed in a semiconductor substrate, the trench having an interior surface and being disposed entirely within a region of the substrate substantially free of germanium,
an outer plate proximate a sidewall of the trench, the outer plate comprising a first conductive material, an insulating layer disposed proximate the outer plate, and
a second conductive material disposed in the trench proximate the insulating layer, the second conductive material defining an inner plate; and
a device formed on the substrate, the device comprising a strained channel.
2. The semiconductor structure of claim 1 , wherein the strained channel comprises strained silicon.
3. The semiconductor structure of claim 1 , wherein the strained channel is disposed proximate a material including SiGe.
4. The semiconductor structure of claim 1 , wherein the device comprises a transistor.
5. The semiconductor structure of claim 4 , wherein the transistor comprises an access transistor.
6. The semiconductor structure of claim 4 , wherein the transistor comprises an NMOS transistor.
7. The semiconductor structure of claim 4 , wherein the transistor comprises a PMOS transistor.
8. The semiconductor structure of claim 1 , wherein strain in the strained channel is induced by a strain-inducing material comprising silicon.
9. The semiconductor structure of claim 7 , further comprising an isolation region proximate the strain-inducing material.
10. The semiconductor structure of claim 8 , wherein the isolation region comprises silicon dioxide.
11. The semiconductor structure of claim 1 , wherein strain in the strained channel is induced by a strain-inducing material comprising germanium.
12. The semiconductor structure of claim 11 , wherein the strain-inducing material is at least partially relaxed.
13. The semiconductor structure of claim 11 , further comprising an isolation region proximate the strain-inducing material.
14. The semiconductor structure of claim 13 , wherein the isolation region comprises silicon dioxide.
15. The semiconductor structure of claim 1 , further comprising a second insulating layer disposed beneath the strained channel.
16. The semiconductor structure of claim 1 , wherein the insulating layer comprises silicon dioxide.
17. The semiconductor structure of claim 1 , wherein the insulating layer comprises nitrided silicon dioxide.
18. The semiconductor structure of claim 1 , wherein the insulating layer comprises an insulating material having a dielectric constant higher than a dielectric constant of silicon dioxide.
19. The semiconductor structure of claim 18 , wherein the insulating material comprises at least one of tantalum oxide and silicon nitride.
20. The semiconductor structure of claim 1 , wherein the first conductive material comprises polysilicon.
21. The semiconductor structure of claim 1 , wherein the second conductive material comprises polysilicon.
22. The semiconductor structure of claim 1 , wherein the outer plate comprises a conductive trench sidewall.
23. The semiconductor structure of claim 22 , wherein the conductive trench sidewall comprises dopants diffused into the trench sidewall.
24. The semiconductor structure of claim 22 , wherein the conductive trench sidewall comprises dopants implanted into the trench sidewall.
25. The semiconductor structure of claim 1 , wherein the strained channel is tensilely strained.
26. The semiconductor structure of claim 1 , wherein the strained channel is compressively strained.