IP Library › Granted Patent US 7,413,925
Granted Patent B2
US 7,413,925 · App. 11/593,039 · Granted Aug 19, 2008

Method for fabricating semiconductor package

Assignee: Oki Electric Inductry Co., Ltd.
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Quick Facts
Patent No.
US 7,413,925
App. No.
11/593,039
Granted
Aug 19, 2008
Kind
B2
Abstract

According to this invention, a method for fabricating a semiconductor package, in which a plurality of semiconductor chips having a through electrode is layered on a semiconductor interposer, comprising: mounting and layering a plurality of semiconductor chips on a first surface of a semiconductor wafer, which is to be used for a semiconductor interposer; forming a mold resin over the semiconductor chips to cover the semiconductor chips entirely; and dicing the semiconductor wafer to form a plurality of individual semiconductor packages.

Claims (17)

1. A method for fabricating a semiconductor package, in which a plurality of semiconductor chips having a through electrode is layered on a semiconductor interposer, comprising:

providing a support member onto a second surface of a semiconductor wafer until at least a resin molding step is complete:

mounting a plurality of semiconductor chips on a first surface of the semiconductor wafer, which is opposite to the second surface, the semiconductor wafer being used for a semiconductor interposer;

forming a mold resin over the semiconductor chips to cover the semiconductor chips entirely; and

dicing the semiconductor wafer to form a plurality of individual semiconductor packages.

2. A method for fabricating a semiconductor package according to claim 1 ,

wherein the support member is a glass plate.

3. A method for fabricating a semiconductor package according to claim 1 , further comprising:

removing the support member after the resin molding step; and

forming external terminals on the second surface of the semiconductor wafer.

4. A method for fabricating a semiconductor package according to claim 1 , further comprising:

forming external terminals on the second surface of the semiconductor wafer before providing the support member onto the second surface.

5. A method for fabricating a semiconductor package according to claim 1 , further comprising:

grinding the first surface of the semiconductor wafer after the support member is provided to the second surface; and

mounting the semiconductor chips on the first surface of the semiconductor wafer, which has been ground.

6. A method for fabricating a semiconductor package according to claim 1 , further comprising:

forming a rewiring layer on the first surface before the semiconductor chips are mounted on the semiconductor wafer.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2022
From: ACHLYS TECHNOLOGIES INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060244/0398 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 11, 2022
From: LAPIS SEMICONDUCTOR CO., LTD.
To: ACHLYS TECHNOLOGIES INC.
Reel/Frame 059559/0280 →
CHANGE OF NAME Recorded Mar 21, 2014
From: OKI SEMICONDUCTOR CO., LTD
To: LAPIS SEMICONDUCTOR CO., LTD.
Reel/Frame 032495/0483 →
CHANGE OF NAME Recorded Jan 16, 2009
From: OKI ELECTRIC INDUSTRY CO., LTD.
To: OKI SEMICONDUCTOR CO., LTD.
Reel/Frame 022162/0586 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2006
From: EGAWA, YOSHIMI
To: OKI ELECTRIC INDUSTRY CO., LTD.
Reel/Frame 018525/0442 →
Priority Claims (1)
JP 2006-030407 · Feb 8, 2006 · national
Continuity (1)
Related Publication 20070184583A1 · Aug 9, 2007