Negative differential resistance field effect transistor for implementing a pull up element in a memory cell
A memory cell includes a storage capacitor and a negative differential resistance (NDR) field effect transistor (FET), wherein the NDR FET is connected between a high voltage source and the storage capacitor. A junction between the NDR FET and the storage capacitor forms a storage node of the memory cell. when a logic HIGH value is stored at the storage node, a pulsed gate bias signal turns on the NDR FET. In contrast, when a logic LOW value is stored at the storage node, the pulsed gate bias signal does not turn on the NDR FET. Thus, using the NDR FET as a pull-up element, the memory cell can exhibit a refresh behavior that is dependent on the data value stored in the memory cell. Moreover, this memory cell can be operated without a separate refresh cycle.
1. A random access memory (RAM) cell comprising:
a storage capacitor; and
a negative differential resistance (NDR) field effect transistor (FET), the NDR FET being coupled between a high voltage supply terminal and the storage capacitor, wherein a junction between the storage capacitor and the NDR FET forms a storage node for the RAM cell.
2. The RAM cell of claim 1 , wherein the NDR FET is an n-channel metal insulator semiconductor (MIS) device.
3. The RAM cell of claim 2 , wherein all transistors in the RAM cell are n-channel devices.
4. The RAM cell of claim 1 , wherein the NDR FET is situated on a silicon-on-insulator (SOI) substrate.
5. A pull-up element for a random access memory (RAM) cell, the RAM cell comprising a storage capacitor, the pull-up element comprising a negative differential resistance (NDR) field effect transistor (FET) coupled between the storage capacitor and a high voltage terminal of the RAM cell,
wherein a junction between the pull-up element and the storage capacitor forms a storage node for the RAM cell, and
wherein a gate of the NDR FET is coupled to receive a pulsed gate bias signal, the pulsed gate bias signal comprising periodic pulses,
wherein when a first voltage potential is stored at the storage node, the periodic pulses cause the NDR FET to be turned on, and
wherein when a second voltage potential is stored at the storage node, the periodic pulses do not cause the NDR FET to be turned on.
6. The pull-up element of claim 5 , wherein the NDR FET is an n-channel device.
7. The pull-up element of claim 5 , wherein the NDR FET does not use band-to-band tunneling to achieve an NDR characteristic.
8. The pull-up element of claim 5 , wherein the NDR FET includes at least one terminal that is shared with a non-NDR silicon based FET within the RAM cell.
9. The pull-up element of claim 5 , wherein the storage capacitor has a first leakage behavior that is greater than a second leakage behavior of the NDR FET when the NDR FET is turned off.
10. A random access memory (RAM) comprising a plurality of memory cells, wherein each of the plurality of memory cells comprises:
a storage capacitor; and
a negative differential resistance (NDR) field effect transistor (FET) coupled between a high voltage supply terminal and the storage capacitor,
wherein a junction between the storage capacitor and the NDR FET forms a storage node for the memory cell.
11. The RAM of claim 10 , further comprising a bias generation circuit for supplying one or more bias signal to a gate of the NDR FET in each memory cell, wherein each of the one or more bias signals comprises periodic pulses to a high bias voltage, the high bias voltage being greater than a standard threshold voltage of the NDR FET in each memory cell.
12. The RAM of claim 11 , wherein the plurality of memory cells are arranged in a plurality of rows, and
wherein the bias generation circuit provides the periodic pulses to the plurality of rows in sequential loop.
13. The RAM of claim 11 , wherein the plurality of memory cells are arranged in a plurality of columns, and
wherein the bias generation circuit provides the periodic pulses to the plurality of columns in sequential loop.
14. The RAM of claim 11 , further comprising a plurality of bit lines and a plurality of word lines,
wherein each of the plurality of memory cells further comprises an access transistor coupled between the storage node and one of the plurality of bit lines,
wherein a gate of the access transistor in each of the plurality of memory cells is coupled to one of the plurality of word lines.
15. The RAM of claim 14 , wherein the NDR FET and the access transistor in each of the plurality of memory cells share a common terminal.