IP Library › Granted Patent US 7,456,096
Granted Patent B2
US 7,456,096 · App. 11/530,724 · Granted Nov 25, 2008

Method of manufacturing silicide layer for semiconductor device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,456,096
App. No.
11/530,724
Granted
Nov 25, 2008
Kind
B2
Abstract

It is made possible to reduce the interface resistance at the interface between the nickel silicide film and the silicon. A semiconductor manufacturing method includes: forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region; depositing a Ni layer so as to cover the impurity region; changing the surface of the impurity region into a NiSi 2 layer through annealing; forming a Ni layer on the NiSi 2 layer; and silicidating the NiSi 2 layer through annealing.

Claims (14)

1. A method of manufacturing a semiconductor device, comprising:

forming an impurity region on a silicon substrate, with impurities being introduced into the impurity region;

depositing a Ni layer so as to cover the impurity region;

changing the surface of the impurity region into a NiSi 2 layer through annealing;

forming a Ni layer on the NiSi 2 layer; and

silicidating the NiSi 2 layer through annealing.

2. The method of manufacturing a semiconductor device as claimed in claim 1 , wherein a film thickness of the Ni layer deposited on the NiSi 2 layer is smaller than a film thickness of the NiSi 2 layer.

3. The method of manufacturing a semiconductor device as claimed in claim 1 , wherein the silicidation of the NiSi 2 layer includes forming a silicide laminated film including a NiSi 2 layer and a NiSi layer.

4. The method of manufacturing a semiconductor device as claimed in claim 1 , wherein the silicidation of the NiSi 2 layer includes performing annealing at a temperature of 500° C. Or lower.

5. The method of manufacturing a semiconductor device as claimed in claim 4 , wherein the silicidation of the NiSi 2 layer includes performing annealing at a temperature of 400° C. Or lower.

6. The method of manufacturing a semiconductor device as claimed in claim 1 , wherein the changing of the surface of the impurity region into a NiSi 2 layer comprising:

changing the surface of the impurity region into a Ni 2 Si layer through annealing;

changing the Ni 2 Si layer into a NiSi layer through annealing; and

changing the NiSi layer into a NiSi 2 layer through annealing.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 4, 2006
From: YAMAUCHI, TAKASHI; KINOSHITA, ATSUHIRO; TSUCHIYA, YOSHINORI; KOGA, JUNJI; KATO, KOICHI; AOKI, NOBUTOSHI; OHUCHI, KAZUYA
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 018663/0769 →
Priority Claims (1)
JP 2005-363813 · Dec 16, 2005 · national
Continuity (1)
Related Publication 20070141836A1 · Jun 21, 2007