Output driver

1. A semiconductor device, comprising:

a first compensator to generate a first compensated signal having a controlled slew rate in response to a first input signal;

a first limiter, coupled to the first compensator, to control operation of the first compensator;

a second compensator to generate a second compensated signal having a controlled slew rate in response to a second input signal;

a second limiter, coupled to the second compensator, to control operation of the second compensator; and

an output device that receives the first compensated signal and the second compensated signal to drive an output signal.

2. A semiconductor device according to claim 1 ,

wherein the first compensator receives a first process supply voltage and temperature (PVT) dependent signal and the second compensator receives a second PVT dependent signal.

3. A semiconductor device, according to claim 2 , further comprising a pre-driver to receive the first and second compensated signal and the data signal to provide a pre-drive signal to an output driver.

4. A semiconductor device according to claim 3 ,

wherein said driver comprises an accelerator device to accelerate the pre-drive signal.

5. A semiconductor device, according to claim 1 , further comprising an input terminal to receive a data signal and an output terminal to provide data to said output.

6. A semiconductor device, according to claim 1 ,

wherein the first compensator is a PMOS compensator and the first limiter is a PMOS limiter.

7. A semiconductor device according to claim 6 ,

wherein the PMOS limiter comprises a current source to provide a limiting current and a NMOS bias transistor.

8. A semiconductor device, according to claim 1 ,

wherein the second compensator is a NMOS compensator and the second limiter is a NMOS limiter.

9. A semiconductor device according to claim 8 ,

wherein the NMOS limiter comprises a current source to provide a limiting current and a NMOS bias transistor.

10. A semiconductor device according to claim 1 ,

wherein said device is a slew rate controller device.

11. Memory system, comprising a semiconductor device according to claim 1 .

12. A semiconductor device, comprising:

a PMOS compensator to generate a PMOS compensated signal and a PMOS limiter to control operation of the PMOS compensator;

a NMOS compensator to generate a NMOS compensated signal and a NMOS limiter to control operation of the NMOS compensator; and

an output driver adapted to receive the PMOS compensated signal and the NMOS compensated signal to drive an output.

13. A semiconductor device according to claim 12 ,

wherein the NMOS compensator and the PMOS compensator compensate process supply voltage and temperature (PVT) variations.

14. A semiconductor device according to claim 12 ,

wherein the PMOS compensator and the NMOS compensator generate substantially PVT dependent signals.

15. A semiconductor device according to claim 12 ,

wherein the NMOS limiter comprises a current source to provide a limiting current which is essentially independent of PVT variations and a NMOS bias transistor.

16. A semiconductor device according to claim 12 ,

wherein the PMOS limiter comprises a current source to provide a limiting current which is essentially independent of PVT variations and a NMOS bias transistor.

17. A method for driving an output of a semiconductor device, comprising:

receiving a first process-voltage-temperature (PVT) signal and a second process-voltage-temperature (PVT) signal;

generating a first compensated signal based on said first process-voltage-temperature (PVT) signal;

generating a second compensated signal based on said second process-voltage-temperature (PVT) signal; and

driving an output according to said first and second compensated signals.

18. Method according to claim 17 , further comprising:

controlling the generation of said first compensated signal; and

controlling the generating of said second compensated signal.

19. Method according to claim 18 , wherein said controlling is based on a corresponding first a second limiting signal, said first and second limiting signals being essentially independent of PVT variations.

20. Method according to claim 18 , wherein said semiconductor device is an integrated memory device.

21. Method according to claim 18 , wherein said semiconductor device is a DRAM device.

22. Memory system according to claim 21 , wherein said system is a fully buffered DIMM memory system having a controller with an integrated semiconductor device according to claim 1 .