Multi-cycle instructions

1. A method comprising:

receiving a multi-cycle instruction in a pipelined processor;

detecting the multi-cycle instruction prior to a decode stage within a pipeline of the pipelined processor;

stalling the multi-cycle instruction in the decode stage; and

issuing a plurality of instructions to subsequent stages in the pipeline while the multi-cycle instruction is stalled.

2. The method of claim 1 further comprising:

deasserting a pre-stall signal at least two cycles prior to the completion of the multi-cycle instruction; and

deasserting a stall signal at least one cycle prior to the completion of the multi-cycle instruction.

3. The method of claim 1 , wherein issuing a plurality of instructions includes issuing the same instruction a number of times when the multi-cycle instruction is stalled.

4. The method of claim 3 , wherein issuing the same instruction a number of times includes issuing a push instruction.

5. The method of claim 1 , wherein issuing a plurality of instructions includes issuing a number of different instructions when the multi-cycle instruction is stalled.

6. The method of claim 5 , wherein issuing a number of different instructions includes issuing instructions to push a return address for a subroutine on a stack, push a frame pointer on the stack, move a stack pointer to the frame pointer and update the stack pointer based on a frame size for the subroutine.

7. The method of claim 1 , wherein issuing a plurality of instructions includes issuing instructions according to a state machine.

8. The method of claim 1 , wherein stalling the multi-cycle instruction comprises asserting a stall signal when the multi-cycle instruction specifies at least one of popping and pushing more than one register.

9. A method comprising:

receiving a multi-cycle instruction directing a pipelined processor to pop one or more registers from a stack;

detecting the multi-cycle instruction prior to a decode stage within a pipeline of the pipelined processor;

stalling the multi-cycle instruction in the decode stage; and

issuing a plurality of instructions to subsequent stages in the pipeline according to a state machine.

10. The method of claim 9 , wherein when the multi-cycle instruction specifies popping two registers, issuing a plurality of instructions comprises:

transitioning from a first state to a second state and issuing an instruction a first pop instruction; and

transitioning from the second state back to the first state and issuing a second pop instruction.

11. The method of claim 9 , wherein when the multi-cycle instruction specifies popping three or more registers from a stack, and issuing a plurality of instructions comprises:

transitioning from a first state to a second state and issuing an instruction a first pop instruction;

issuing a number of pop instructions until two registers remain to be popped;

transitioning from the second state to a third state and issuing another pop instruction to pop the second to last register; and

transitioning from the third state back to the first state and issuing a pop instruction to pop the last register.

12. The method of claim 9 , wherein when the multi-cycle instruction specifies popping multiple data registers and multiple pointer registers from a stack, and issuing a plurality of instructions comprises:

transitioning from a first state to a second state and issuing an instruction a first instruction to pop a pointer register;

issuing a number of pop instructions until one pointer register remains to be popped;

transitioning from the second state to a third state and issuing another pop instruction to pop the final pointer register;

issuing a number of pop instructions until two data registers remains to be popped;

transitioning from the third state to a fourth state and issuing a pop instruction to pop the second to last data register; and

transitioning from the fourth state back to the first state and issuing a pop instruction to pop the last data register.

13. The method of claim 9 , wherein stalling the multi-cycle instruction comprises asserting a stall signal when the multi-cycle instruction specifies popping more than one register.

14. A method comprising:

receiving a multi-cycle instruction directing a pipelined processor to push one or more registers on a stack;

detecting the multi-cycle instruction prior to a decode stage within a pipeline of the pipelined processor;

stalling the multi-cycle instruction in the decode stage; and

issuing a plurality of push instructions to subsequent stages in the pipeline according to a state machine.

15. The method of claim 14 , wherein when the multi-cycle instruction specifies pushing two registers and issuing a plurality of instructions comprises:

transitioning from a first state to a second state and issuing a first push instruction; and

transitioning from the second state back to the first state and issuing a second push instruction.

16. The method of claim 14 , wherein when the multi-cycle instruction specifies pushing three or more registers on stack, issuing a plurality of instructions comprises:

transitioning from a first state to a second state and issuing an instruction a first push instruction;

issuing a number of push instructions until two registers remain to be pushed;

transitioning from the second state to a third state and issuing another push instruction to push the second to last register; and

transitioning from the third state back to the first state and issuing a push instruction to push the last register.

17. The method of claim 14 , wherein when the multi-cycle instruction specifies pushing multiple data registers and multiple pointer registers on a stack, and issuing a plurality of instructions comprises:

transitioning from a first state to a second state and issuing an instruction a first instruction to push a data register;

issuing a number of push instructions until one data register remains to be pushed;

transitioning from the second state to a third state and issuing another push instruction to push the final data register;

issuing a number of push instructions until two pointer registers remains to be pushed;

transitioning from the third state to a fourth state and issuing a push instruction to push the second to last pointer register; and

transitioning from the fourth state back to the first state and issuing a push instruction to push the last pointer register.

18. The method of claim 14 , wherein stalling the multi-cycle instruction comprises asserting a stall signal when the multi-cycle instruction specifies pushing more than one registers.

19. An apparatus comprising:

an execution pipeline having a plurality of stages including a decode stage; and

a multi-cycle instruction (MCI) controller adapted to detect a multi-cycle instruction prior to the decode stage and assert a stall signal to stall the multi-cycle instruction entering the decode stage of the execution pipeline, wherein the MCI controller issues a plurality of instructions to subsequent stages in the pipeline when the multi-cycle instruction is stalled.

20. The apparatus of claim 19 further comprising a stall controller receiving the MCI controller stall signal from the MCI controller and generating a plurality of stall signals to stall the decode stage holding the multi-cycle instruction and prior stages in the pipeline.

21. The apparatus of claim 19 , wherein the MCI controller is adapted to issue the same instruction a number of times when the multi-cycle instruction is stalled.

22. The apparatus of claim 19 , wherein the MCI controller is adapted to issue a push instruction to direct the pipeline to push a plurality of registers.

23. The apparatus of claim 19 , wherein the MCI controller is adapted to issue a number of different instructions when the multi-cycle instruction is stalled.

24. The apparatus of claim 19 , wherein the MCI controller is adapted to issue instructions to push a return address for a subroutine on a stack, push a frame pointer on the stack, move a stack pointer to the frame pointer and update the stack pointer based on a frame size for the subroutine.

25. The apparatus of claim 19 , wherein the MCI controller asserts the stall signal when the multi-cycle instruction specifies either popping or pushing more than one registers.

26. A system comprising:

a Flash memory device; and

a processor coupled to the Flash memory device, wherein the processor includes an execution pipeline having a plurality of stages, including a decode stage, and a multi-cycle instruction (MCI) controller adapted to detect a multi-cycle instruction prior to the decode stage and assert a stall signal to stall the multi-cycle instruction within the decode stage of the execution pipeline; wherein the MCI controller is adapted to issue a plurality of instructions to subsequent stages in the pipeline when the multi-cycle instruction is stalled.

27. The system of claim 26 , wherein the processor further comprises a stall controller receiving the MCI controller stall signal from the MCI controller and generating a plurality of stall signals to stall the decode stage holding the multi-cycle instruction and prior stages in the pipeline.

28. The system of claim 26 , wherein the MCI controller is adapted to issue the same instruction a number of times when the multi-cycle instruction is stalled.

29. The system of claim 26 , wherein the MCI controller is adapted to issue a number of different instructions when the multi-cycle instruction is stalled.

30. The system of claim 26 , wherein the MCI controller asserts the stall signal when the multi-cycle instruction specifies at least one of popping and pushing more than one registers.

31. A method comprising:

receiving a link machine instruction;

detecting the multi-cycle instruction prior to a decode stage within a pipeline of a pipelined processor;

stalling the multi-cycle instruction in the decode stage; and

executing the link instruction by issuing a plurality of instructions to subsequent stages in the pipeline according to a state machine.

32. The method of claim 31 , wherein issuing a plurality of instructions comprises:

transitioning from a first state to a second state and issuing an instruction to push a return address on a stack;

transitioning from the second state to a third state and issuing an instruction to push a frame pointer on the stack;

transitioning from the third state to a fourth state and issuing an instruction to move a stack pointer to the frame pointer; and

transitioning from the fourth state back to the first state and issuing an instruction to update a stack pointer based on a frame size specified by the multi-cycle machine instruction.

33. A method comprising:

receiving an unlink machine instruction;

detecting the multi-cycle instruction prior to a decode stage within a pipeline of a pipelined processor;

stalling the multi-cycle instruction in the decode stage; and

executing the unlink instruction by issuing a plurality of instructions to subsequent stages in the pipeline according to a state machine.

34. The method of claim 33 , wherein issuing a plurality of instructions comprises:

transitioning from a first state to a second state and issuing an instruction to restore a return address from a stack;

transitioning from the second state to a third state and issuing an instruction to restore a stack pointer; and

transitioning from the third state back to the first state and issuing an instruction to restore a frame pointer from the stack.

35. An apparatus comprising:

state machine logic to control the issuing of a plurality of sub-operations in a pipelined processor in response to a multi-cycle machine instruction being received and stalled in a decode stage within the pipelined processor where the multi-cycle instruction is first detected prior to the decode stage; and

an address generation unit adapted to generate register addresses for use during the execution of the sub-operations.

36. The apparatus of claim 35 , wherein the address generation unit comprises a counter for incrementing or decrementing a current register address.

37. The apparatus of claim 35 , wherein the address generation unit comprising a clocked storage circuit to store a current register address.