DRAM cells with vertical transistors

1. A method for forming a transistor for an integrated circuit, the method comprising:

etching a semiconductor substrate to form a U-shaped silicon pillar pair and etched regions surrounding the U-shaped silicon pillar pair, wherein the silicon pillar pair comprises a first pillar and a second pillar;

forming a first source/drain region in the first pillar;

forming a second source/drain region in the second pillar; and

forming a gate line in at least a portion of the etched regions, wherein the gate line at least partially surrounds the first and second pillars, wherein the first source/drain region, the second source/drain region, and at least a portion of the gate line form a U-shaped transistor.

2. The method of claim 1 further comprising forming a dielectric layer on the U-shaped silicon pillar pair within at least a portion of the etched regions, wherein the dielectric layer at least partially surrounds the first and second pillars.

3. The method of claim 1 further comprising forming a metal layer on the gate line and performing a self-aligned salicide process on the metal layer.

4. The method of claim 1 further comprising filling at least a portion of the etched regions with an oxide-containing material.

5. A method for forming a semiconductor device, the method comprising:

etching a first set of trenches to a first depth into a semiconductor substrate;

etching a second set of trenches to a second depth into the semiconductor substrate, wherein the first set of trenches is substantially parallel to the second set of trenches, and wherein the first set of trenches and the second set of trenches are alternately spaced from one another within the semiconductor substrate;

etching a third set of trenches to a third depth into the semiconductor substrate, wherein the third set of trenches is substantially orthogonal to the first set of trenches and to the second set of trenches;

wherein the first, second, and third sets of trenches define an array of vertically extending pillars, wherein the array of vertically extending pillars comprises vertical source/drain regions, and wherein the third depth is greater than the first depth and less than the second depth; and

forming a gate line within at least a portion of the third set of trenches, wherein the gate line and the vertical source/drain regions form a plurality of transistors in which pairs of the source/drain regions are connected to one another through a transistor channel.

6. The method of claim 5 further comprising filling at least a portion of the first set of trenches with an oxide-containing material.

7. The method of claim 5 further comprising filling at least a portion of the first set of trenches with a conductive gate material.

8. The method of claim 5 further comprising filling at least a portion of the second set of trenches with an oxide-containing material.

9. The method of claim 5 , wherein the gate line comprises a gate electrode layer and a metallic layer.

10. The method of claim 9 , wherein the metallic layer comprises a metal silicide.

11. The method of claim 5 , wherein each of the transistors comprises a first source/drain region electrically connected to a digit line and a second source/drain region electrically connected to a memory storage device.

12. The method of claim 5 , wherein the first set of trenches and the second set of trenches are etched prior to etching the third set of trenches.

13. A method for forming a memory array, the method comprising:

applying a device mask to a semiconductor substrate to form a first pattern of alternating first lines and first gaps on the semiconductor substrate;

processing the semiconductor substrate to form a first set of trenches, wherein the first set of trenches are formed within the semiconductor substrate within at least a portion of the area defined by the first gaps;

applying a periphery mask to the semiconductor device after forming the first set of trenches, wherein the periphery mask protects a periphery adjacent an array region;

processing the semiconductor substrate to form a second set of trenches substantially parallel to the first set of trenches, wherein the second set of trenches are formed within the semiconductor substrate within at least a portion of the array region;

applying a wordline mask to the semiconductor device to form a second pattern of alternating second lines and second gaps on the semiconductor substrate after forming the second set of trenches, wherein the second lines and second gaps intersect with paths of the first lines and first gaps; and

processing the semiconductor substrate to form a third set of trenches, wherein the third set of trenches are formed within the semiconductor substrate within at least a portion of the area defined by the second gaps, and not formed in the protected periphery.

14. The method of claim 13 further comprising forming an epitaxial silicon layer on the semiconductor substrate prior to applying the first mask.

15. The method of claim 13 further comprising forming an array of pillars within the semiconductor substrate within at least a portion of the area defined by the second lines.

16. The method of claim 15 , wherein the pillars comprise vertical source/drain regions.

17. The method of claim 13 further comprising forming a gate line in at least a portion of the third set of trenches.

18. The method of claim 17 , wherein pairs of pillars defined by the trenches form U-shaped transistors, wherein each pillar in the pair of pillars is separated by one trench of the first set of trenches, and wherein each U-shaped transistor is separated from an adjacent U-shaped transistor by one trench of the second set of trenches.

19. The method of claim 18 , wherein each of the transistors comprises a first source/drain region and a second source/drain region at the tops of the pair of pillars.

20. The method of claim 19 further comprising:

electrically connecting a digit line to the first source/drain region of each of the transistors; and

electrically connecting a memory storage device to the second source/drain region of each of the transistors.

21. The method of claim 20 , wherein the memory storage device is a capacitor.

22. The method of claim 18 , wherein a column of the U-shaped transistors surrounded by the gate line in the trenches of the third set of trenches on either side of the column form a wordline.

23. A method of forming a semiconductor structure comprising:

etching a set of wordline trenches within a semiconductor substrate;

etching a set of deep trenches within a semiconductor substrate, the set of deep trenches crossing and creating a grid with the set of wordline trenches, wherein the deep trenches are deeper than the wordline trenches, and wherein the set of wordline trenches and the set of deep trenches define a plurality of protrusions within the semiconductor substrate;

defining a heavily doped region and a lightly doped region within each protrusion;

depositing gate material into the set of wordline trenches; and

spacer etching the gate material to define a gate electrode on sidewalls of the protrusion.

24. The method of claim 23 , wherein the gate electrode is only formed on opposite sidewalls of the protrusion.

25. The method of claim 23 further comprising etching a shallow trench into each protrusion to form a U-shaped protrusion comprising a first pillar, a second pillar, and a base, wherein the shallow trench is substantially parallel to the set of deep trenches.

26. The method of claim 25 , wherein the heavily doped region forms source/drain regions at the tops of the pillars and the lightly doped region forms a U-shaped channel extending from lower parts of the pillars and across the base.

27. The method of claim 25 , wherein defining doped regions comprises doping the semiconductor substrate prior to etching.