Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility
A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer ( 26 ) formed over a substrate ( 11 ), thereby forming etched gates ( 62, 64 ) having vertical sidewall profiles ( 61, 63 ). While a blanket nitrogen implant ( 46 ) of the intrinsic polysilicon layer ( 26 ) may occur prior to gate etch, more idealized vertical gate sidewall profiles ( 61, 63 ) are obtained by fully doping the gates ( 80, 100 ) during the source/drain implantation steps ( 71, 77, 91, 97 ) and after the gate etch.
1. A method for forming a semiconductor device comprising:
providing a semiconductor substrate;
forming a dielectric layer over the semiconductor substrate;
forming an undoped layer over the dielectric layer;
implanting nitrogen into the undoped layer;
selectively etching the undoped layer after implanting nitrogen with an anisotropic etch process chemistry, thereby forming a plurality of etched gates having implanted nitrogen and having substantially vertical sidewalls;
selectively implanting a first etched gate and the substrate in a first circuit area with a first dopant species to simultaneously dope the first etched gate and form first source/drain regions; and
selectively implanting a second etched gate and the substrate in a second circuit area with a second dopant species to simultaneously dope the second etched gate and form second source/drain regions.
2. The method of claim 1 , further comprising selectively implanting a third dopant species into the undoped layer in a third circuit area to form a doped layer prior to selectively etching said doped layer.
3. The method of claim 2 , where the first etched gate in the first circuit area is used to form a core PMOS transistor, the second etched gate in the second circuit area is used to form a core NMOS transistor, and the doped layer in the third circuit area is used to form a transistor having a gate length that is larger than a gate length of the core PMOS transistor or core NMOS transistor.
4. The method of claim 1 , where the anisotropic etch process chemistry comprises flowing between about 8 sccm and 12 sccm of O 2 and between about 8 sccm and 12 sccm of CF 4 into a processing chamber.
5. The method of claim 1 , where selectively etching comprises a plasma etch process.
6. The method of claim 2 , where polysilicon resistors are formed in the third circuit area by selectively etching the doped layer.
7. The method of claim 2 , where input/output transistors are formed by selectively etching the doped layer in the third circuit area.
8. The method of claim 1 , where selectively implanting a first etched gate comprises:
forming first sidewall spacers on the vertical sidewalls of the first etched gate; and
using a first implant which dopes the first etched gate and forms first source/drain regions in exposed regions of the substrate.
9. The method of claim 1 , where selectively implanting a first etched gate comprises:
forming first sidewall spacers on the vertical sidewalls of the first etched gate;
using a first implant which dopes the first etched gate and forms first source/drain regions in exposed regions of the substrate;
forming second sidewall spacers on the first sidewall spacers; and
using a second implant which dopes the first etched gate and forms second source/drain regions in the substrate spaced apart from the vertical sidewalls of the first etched gate by the first and second sidewall spacers.
10. The method of claim 1 , where the undoped layer comprises a layer of undoped polysilicon.
11. A method for forming a semiconductor device, comprising:
forming a dielectric layer over a semiconductor substrate;
forming an undoped polysilicon layer over the dielectric layer in first, second and third circuit areas;
selectively implanting a predetermined dopant species into the undoped polysilicon layer in the third circuit area;
selectively etching the polysilicon layer with an anisotropic etch process chemistry to form a plurality of etched gates in the first and second circuit areas, said etched gates having substantially vertical sidewalls;
selectively implanting a first etched gate and the substrate in the first circuit area with a first dopant species to simultaneously dope the first etched gate and form first source/drain regions;
selectively implanting a second etched gate and the substrate in the second circuit area with a second dopant species to simultaneously dope the second etched gate and form second source/drain regions.
12. The method of claim 11 , where the plurality of etched gates are used to form MOSFET transistor devices.
13. The method of claim 11 , where the plurality of etched gates are used to form FinFET transistor devices.
14. The method of claim 11 , where selectively implanting a first etched gate comprises:
forming first sidewall spacers on the sidewalls of the first etched gate;
using a first implant which dopes the first etched gate and forms first source/drain regions in exposed regions of the substrate;
forming second sidewall spacers on the first sidewall spacers; and
using a second implant which dopes the first etched gate and forms second source/drain regions in the substrate spaced apart from the vertical sidewalls of the first etched gate by the first and second sidewall spacers.
15. The method of claim 11 , where the anisotropic etch process comprises a plasma etch process.
16. The method of claim 11 , further comprising implanting nitrogen into the undoped polysilicon layer in the first and second circuit areas before selectively etching the polysilicon layer.
17. The method of claim 11 , further comprising selectively implanting nitrogen into the undoped polysilicon layer in the first circuit area after selectively etching the polysilicon layer.
18. A method of fabricating a gate electrode, comprising:
selectively etching an undoped polysilicon layer in a first predetermined circuit area to form an etched gate electrode having substantially vertical sidewalls;
implanting nitrogen into the etched gate electrode and any unprotected substrate regions; and
selectively implanting the etched gate electrode and the unprotected substrate regions with a first dopant species to simultaneously dope the etched gate electrode and form first source/drain regions in the substrate adjacent the etched gate electrode.
19. The method of claim 18 , further comprising:
selectively implanting a predetermined dopant species into the undoped polysilicon layer in a second predetermined circuit area prior to selectively etching the undoped polysilicon layer; and
selectively etching the polysilicon layer in the second predetermined circuit area to form polysilicon resistors or non-core transistor gates.
20. The method of claim 18 , further comprising forming sidewall spacers on the vertical sidewalls of the etched gate electrode prior to implanting nitrogen into the etched gate electrode.