Two-bit tri-level forced transition encoding
An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between ‘−1’ and ‘0’ logic states, or ‘+1’ and ‘0’ logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep.
1. A method for encoding a sequence of data bits, comprising:
providing two original consecutive bits from the sequence of data bits, wherein each of the two original consecutive bits has one of two potential logic levels, and wherein each of the two original consecutive bits has a duration;
converting the two original consecutive bits into two encoded consecutive bits by assessing the logic levels of the original consecutive bits, wherein if the two original consecutive bits are of the same level then the two encoded consecutive bits comprise a first and second of three potential logic levels, and if the two original consecutive bits are not of the same level then the two encoded consecutive bits comprise the second and a third of the three potential logic levels, wherein the second logic level is between the first and third logic levels, and wherein each of the two encoded consecutive bits has the duration; and
repeating the foregoing steps for a next two original consecutive bits from the sequence of data bits.
2. The method of claim 1 , wherein the three potential logic levels for the encoded consecutive bits comprise a negative power supply voltage, a ground voltage, and a positive power supply voltage.
3. The method of claim 1 , wherein the three potential logic levels for the encoded consecutive bits comprise ground, a first positive voltage, and a second positive voltage greater than the first positive voltage.
4. The method of claim 3 , wherein the first positive voltage comprises one-half a power supply voltage, and wherein the second positive voltage comprises the power supply voltage.
5. The method of claim 1 ,
wherein if the two original consecutive bits comprises two logic ‘0’s then the two encoded consecutive bits comprise the first logic level followed by the second logic level,
wherein if the two original consecutive bits comprise two logic ‘1’s then the two encoded consecutive bits comprise the second logic level followed by the first logic level,
wherein if the two original consecutive bits comprises a logic ‘0’ followed by a logic ‘1’ then the two encoded consecutive bits comprise the second logic level followed by the third logic level, and
wherein if the two original consecutive bits comprise a logic ‘1’ followed by a logic ‘0’ then the two encoded consecutive bits comprise the third logic level followed by the second logic level.
6. The method of claim 1 ,
wherein if the two original consecutive bits comprises two logic ‘0’s then the two encoded consecutive bits comprise the second logic level followed by the first logic level,
wherein if the two original consecutive bits comprise two logic ‘1’s then the two encoded consecutive bits comprise the first logic level followed by the second logic level,
wherein if the two original consecutive bits comprises a logic ‘0’ followed by a logic ‘1’ then the two encoded consecutive bits comprise the third logic level followed by the second logic level, and
wherein if the two original consecutive bits comprise a logic ‘1’ followed by a logic ‘0’ then the two encoded consecutive bits comprise the second logic level followed by the third logic level.
7. The method of claim 1 , wherein the second logic level is a midpoint voltage level between the first and third logic levels.
8. A method for transmitting data from a transmitter to a receiver via a channel, comprising:
providing two original consecutive bits from a sequence of data bits in the transmitter, wherein each of the two original consecutive bits has one of two potential logic levels, and wherein each of the two original consecutive bits has a duration;
converting in the transmitter the two original consecutive bits into two encoded consecutive bits by assessing the logic levels of the original consecutive bits, wherein if the two original consecutive bits are of the same level then the two encoded consecutive bits comprise a first and second of three potential logic levels, and if the two original consecutive bits are not of the same level then the two encoded consecutive bits comprise the second and a third of the three potential logic levels, wherein the second logic level is between the first and third logic levels, and wherein each of the two encoded consecutive bits has the duration;
transmitting the two encoded consecutive bits through the channel to the receiver;
receiving the two encoded consecutive bits at the receiver;
decoding in the receiver the two encoded consecutive bits to reconstitute the two original consecutive bits; and
repeating the foregoing steps for a next two original consecutive bits from the sequence of data bits.
9. The method of claim 8 , wherein the three potential logic levels for the encoded consecutive bits comprise a negative power supply voltage, a ground voltage, and a positive power supply voltage.
10. The method of claim 8 , wherein the three potential logic levels for the encoded consecutive bits comprise ground, a first positive voltage, and a second positive voltage greater than the first positive voltage.
11. The method of claim 10 , wherein the first positive voltage comprises one-half a power supply voltage, and wherein the second positive voltage comprises the power supply voltage.
12. The method of claim 8 ,
wherein if the two original consecutive bits comprises two logic ‘0’s then the two encoded consecutive bits comprise the first logic level followed by the second logic level,
wherein if the two original consecutive bits comprise two logic ‘1’s then the two encoded consecutive bits comprise the second logic level followed by the first logic level,
wherein if the two original consecutive bits comprises a logic ‘0’ followed by a logic ‘1’ then the two encoded consecutive bits comprise the second logic level followed by the third logic level, and
wherein if the two original consecutive bits comprise a logic ‘1’ followed by a logic ‘0’ then the two encoded consecutive bits comprise the third logic level followed by the second logic level.
13. The method of claim 8 ,
wherein if the two original consecutive bits comprises two logic ‘0’s then the two encoded consecutive bits comprise the second logic level followed by the first logic level,
wherein if the two original consecutive bits comprise two logic ‘1’s then the two encoded consecutive bits comprise the first logic level followed by the second logic level,
wherein if the two original consecutive bits comprises a logic ‘0’ followed by a logic ‘1’ then the two encoded consecutive bits comprise the third logic level followed by the second logic level, and
wherein if the two original consecutive bits comprise a logic ‘1’ followed by a logic ‘0’ then the two encoded consecutive bits comprise the second logic level followed by the third logic level.
14. The method of claim 8 , wherein the second logic level is a midpoint voltage level between the first and third logic levels.
15. The method of claim 8 , wherein either the transmitter or receiver comprises a synchronous dynamic random access memory.
16. A transmitter, comprising:
an encoder,
wherein the encoder is adapted to continually take a next of two original consecutive bits from a sequence of data bits, wherein each of the two original consecutive bits has a duration, and
wherein the encoder is adapted to convert the two original consecutive bits into two encoded consecutive bits, wherein if the two original consecutive bits are of the same level then the two encoded consecutive bits comprise a first and second of three potential logic levels, and if the two original consecutive bits are not of the same level then the two encoded consecutive bits comprise the second and a third of the three potential logic levels, wherein the second logic level is between the first and third logic levels, and wherein each of the two encoded consecutive bits has the duration, and
wherein the continuous operation of the encoder produces a sequence of encoded bits.
17. The transmitter of claim 16 , wherein the three potential logic levels for the encoded consecutive bits comprise a negative power supply voltage, a ground voltage, and a positive power supply voltage.
18. The transmitter of claim 16 , wherein the three potential logic levels for the encoded consecutive bits comprise ground, a first positive voltage, and a second positive voltage greater than the first positive voltage.
19. The transmitter of claim 18 , wherein the first positive voltage comprises one-half a power supply voltage, and wherein the second positive voltage comprises the power supply voltage.
20. The transmitter of claim 16 , wherein the transmitter is adapted to operate with a clock with a period of twice the duration.
21. The transmitter of claim 16 , wherein the encoder comprises a group formation stage for capturing the next of two original consecutive bits, wherein the group formation stage is coupled to an encoding stage, and wherein the encoding stage is coupled to a driving stage for providing the sequence of encoded bits to a transmission channel.
22. The transmitter of claim 16 ,
wherein if the two original consecutive bits comprises two logic ‘0’s then the two encoded consecutive bits comprise the first logic level followed by the second logic level,
wherein if the two original consecutive bits comprise two logic ‘1’s then the two encoded consecutive bits comprise the second logic level followed by the first logic level,
wherein if the two original consecutive bits comprises a logic ‘0’ followed by a logic ‘1’ then the two encoded consecutive bits comprise the second logic level followed by the third logic level, and
wherein if the two original consecutive bits comprise a logic ‘1’ followed by a logic ‘0’ then the two encoded consecutive bits comprise the third logic level followed by the second logic level.
23. The transmitter of claim 16 ,
wherein if the two original consecutive bits comprises two logic ‘0’s then the two encoded consecutive bits comprise the second logic level followed by the first logic level,
wherein if the two original consecutive bits comprise two logic ‘1’s then the two encoded consecutive bits comprise the first logic level followed by the second logic level,
wherein if the two original consecutive bits comprises a logic ‘0’ followed by a logic ‘1’ then the two encoded consecutive bits comprise the third logic level followed by the second logic level, and
wherein if the two original consecutive bits comprise a logic ‘1’ followed by a logic ‘0’ then the two encoded consecutive bits comprise the second logic level followed by the third logic level.
24. The transmitter of claim 16 , wherein the second logic level is a midpoint voltage level between the first and third logic levels.