Multilayer OPC for design aware manufacturing
View Patent ↗A method is provided for designing a mask layout for an integrated circuit that ensures proper functional interaction among circuit features by including functional inter-layer and intra-layer constraints on the wafer. The functional constraints used according to the present invention are applied among the simulated wafer images to ensure proper functional interaction, while relaxing or eliminating the EPE constraints on the location of the wafer images.
1. A method of designing a mask layout for an integrated circuit, the method comprising the steps of:
providing a plurality of mask shapes corresponding to a plurality of layers;
providing lithographic models for said plurality of layers, said models describing processes according to which wafer images are transferred from said mask shapes to a wafer;
determining simulated wafer images resulting from transferring said plurality of mask shapes in accordance with said models;
providing constraints comprising functional constraints that ensure proper functional interaction among said simulated wafer images;
evaluating said simulated wafer images relative to other of said simulated wafer images and if said constraints are violated, modifying said mask layout to correct said violations;
providing target images representing desired wafer images on said wafer; and
providing edge placement error constraints for said simulated wafer images relative to said target images;
and wherein the step of evaluating said simulated wafer images relative other of said simulated wafer images further comprises evaluating said simulated wafer images relative to said target images, wherein said functional constraints have higher priority than said edge placement error constraints.
2. A computer program product comprising a computer usable medium having a computer readable program embodied in said medium for designing a mask layout for an integrated circuit, wherein the computer readable program when executed on a computer causes the computer to perform the steps of:
providing a plurality of mask shapes corresponding to a plurality of layers;
providing lithographic models for said plurality of layers, said models describing processes according to which wafer images are transferred from said mask shapes to a wafer;
determining simulated wafer images resulting from transferring said plurality of mask shapes in accordance with said models;
providing constraints comprising functional constraints that ensure proper functional interaction among said simulated wafer images;
evaluating said simulated wafer images relative to other of said simulated wafer images and if said constraints are violated, modifying said mask layout to correct said violations;
providing target images representing desired wafer images on said wafer; and
providing edge placement error constraints for said simulated wafer images relative to said target images;
and wherein the step of evaluating said simulated wafer images relative other of said simulated wafer images further comprises evaluating said simulated wafer images relative to said target images, wherein said functional constraints have higher priority than said edge placement error constraints.
3. A method of optimizing a mask layout for an integrated circuit, wherein the mask layout includes a plurality of mask shapes corresponding to a plurality of layers, and the processes of transferring the plurality of mask shapes to a wafer is described by a set of lithographic models, the method comprising the steps of:
determining simulated wafer images resulting from transferring said plurality of mask shapes in accordance with said models;
providing constraints comprising functional constraints that ensure proper functional interaction among said simulated wafer images;
evaluating said simulated wafer images relative to other of said simulated wafer images and if said constraints are violated, modifying said mask layout to correct said violations;
providing target images representing desired wafer images on said wafer; and
determining edge placement error constraints for said simulated wafer images relative to said target images;
and wherein the step of evaluating said simulated wafer images relative other of said simulated wafer images further comprises evaluating said simulated wafer images relative to said target images, wherein said functional constraints have higher priority than said edge placement error constraints.