Granted Patent B2

US 7,504,289 · App. 11/258,781 · Granted Mar 17, 2009

Assignee: Freescale Semiconductor, Inc.

Abstract

Claims (29)

1. A process for forming an electronic device comprising:

providing a substrate;

forming a first gate electrode of a first transistor structure over the substrate, wherein the first transistor structure includes a first channel region;

forming a second gate electrode of a second transistor structure over the substrate, wherein the second transistor structure includes a second channel region that has a conductivity type opposite that of the first channel region;

forming a first sidewall spacer that surrounds the first gate electrode and a second sidewall spacer that surrounds the second gate electrode, wherein the first and second sidewall spacers have a first stress;

removing the second sidewall spacer; and

forming a third sidewall spacer that surrounds the second gate electrode, wherein:

forming the third sidewall spacer comprises:

forming a tensile silicon nitride layer over the first gate electrode, the second gate electrode, the first sidewall spacer, and the substrate; and

removing a portion of the tensile silicon nitride layer using an HF solution;

the third sidewall spacer is formed after removing the second sidewall spacer and has a second stress different from the first stress; and

after forming the third sidewall spacer:

the first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode; and

the third sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode.

2. The process of claim 1 , wherein:

the first transistor structure is a p-channel transistor structure;

the second transistor substrate is an n-channel transistor structure; and

the first stress has a lower value as compared to the second stress.

3. The process of claim 2 , wherein forming the third sidewall spacer comprises forming a mask including an opening, wherein:

the portion of the tensile silicon nitride layer overlies the first gate electrode and the first sidewall spacer is exposed along a bottom of the opening;

the mask covers the second gate electrode; and

removing the exposed portion of the tensile silicon nitride layer is performed after forming the mask.

4. The process of claim 3 , wherein forming the first and second sidewall spacers comprises forming the first and second sidewall spacers that include a compressive silicon nitride layer.

5. The process of claim 4 , wherein removing the exposed portion of the tensile silicon nitride layer comprises removing the exposed portion of the tensile silicon nitride layer, such that the HF solution has a selectivity, wherein tensile silicon nitride can be etched at least approximately 6 times faster than compressive silicon nitride.

6. The process of claim 1 , further comprising forming a liner layer after forming the first gate electrode, after forming the second gate electrode, and before forming the first and second sidewall spacers.

7. The process of claim 1 , wherein:

forming the first gate electrode further comprises forming the first gate electrode, wherein the first active region has a first primary surface;

forming the second gate electrode further comprises forming the second gate electrode, wherein the second active region has a second primary surface; and

channel lengths of each of the first and second transistor structures lies substantially along at least one <110> crystal direction.

Assignments (30)

Continuity (1)