Shallow trench isolation process
A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor.
1. A structure comprising:
a first transistor disposed over a first region of a substrate, the first transistor including:
a first source region and a first drain region disposed in a first portion of the substrate,
a first channel region disposed between the first source region and the first drain region, at least a portion of the first channel region located in a strained layer disposed over the substrate and lattice-mismatched to a proximate material inducing a first type of strain in the strained layer, the first channel region having the first type of strain, and
a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material; and
a first trench structure disposed in a trench,
wherein the trench is proximate at least one side of one of the first source region and the first drain region, the first trench structure inducing a portion of the first type of strain in the first channel region.
2. The structure of claim 1 , wherein the strained layer comprises at least one of a group II, group III, group V, and group VI element.
3. A method for forming a semiconductor structure, the method comprising:
forming a first transistor over a first region of a substrate having a strained layer disposed thereover, the strained layer being lattice-mismatched to a proximate material inducing a first type of strain in the strained layer, the first transistor formed by:
defining a first source region and a first drain region in a first portion of the substrate,
defining a first channel region between the first source region and the first drain region, the first channel region having a first type of strain, at least a portion of the first channel region being disposed in the strained layer, and
forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material;
forming a first trench proximate at least one side of one of the first source region and the first drain region; and
forming a first trench structure in the first trench, the first trench structure being tailored to induce only a portion of the first type of strain in the first channel region.
4. A method for forming a semiconductor structure, the method comprising:
providing a substrate;
forming a first transistor over a first region of the substrate by:
defining a first source region and a first drain region in a first portion of the substrate,
defining a first channel region between the first source region and the first drain region, the first channel region having a first type of strain, and
forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material;
forming a first trench proximate at least one side of one of the first source region and the first drain region; and
forming a first trench structure in the first trench, the first trench structure being tailored to induce only a portion of the first type of strain in the first channel region,
wherein the gate induces at least a second portion of the first type of strain in the first channel region, and forming the first gate comprises (i) forming a polycrystalline semiconductor layer over the substrate and (ii) reacting the polycrystalline semiconductor layer with a metal, such that the first gate consists essentially of an alloy of the metal and the semiconductor layer.
5. The structure of claim 1 , further comprising:
a dielectric layer disposed beneath the first channel region.
6. The structure of claim 1 wherein at least one of the first source region and the first drain region comprises a metal-semiconductor alloy, and the strain in the first channel region is induced by the metal-semiconductor alloy.
7. The structure of claim 1 wherein the first transistor is disposed in a chip, the structure further comprising:
a package housing the chip,
wherein the package induces strain in the first channel region.
8. The method of claim 3 , further comprising:
forming a metal-semiconductor alloy over at least one of the first source region and the first drain region, the metal-semiconductor alloy tailored to induce the first type of strain in the first channel region.
9. The method of claim 4 further comprising, after forming the first gate, depositing an overlayer over the first gate, and annealing the first gate, wherein the first gate consists essentially of the alloy of the metal and the semiconductor layer.
10. A method for forming a semiconductor structure, the method comprising:
providing a substrate;
forming a first transistor over a first region of the substrate by:
defining a first source region and a first drain region in a first portion of the substrate,
defining a first channel region between the first source region and the first drain region, the first channel region having a first type of strain, and
forming a first gate above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material;
forming a first trench proximate at least one side of one of the first source region and the first drain region;
forming a first trench structure in the first trench, the first trench structure being tailored to induce only a portion of the first type of strain in the first channel region;
disposing the first transistor in a chip; and
attaching the chip to a package,
wherein the package induces at least a portion of the first type of strain in the first channel region and the first type of strain is selected from the group consisting of tensile strain and compressive strain.
11. A method for forming a semiconductor structure, the method comprising:
providing a substrate comprising a strained layer having a first type of strain;
forming a masking layer over the substrate such that the masking layer exerts a second type of strain different from the first type of strain on the strained layer;
removing the masking layer over a first portion of the substrate; and
etching a trench in the first portion of the substrate,
wherein the first type of strain is opposite to the second type of strain.
12. The method of claim 11 wherein the masking layer comprises silicon nitride.
13. The method of claim 11 , further comprising forming a pad oxide layer over the substrate prior to forming the masking layer.
14. A structure comprising:
a first transistor disposed over a first region of a substrate, the first transistor including:
a first source region and a first drain region disposed in a first portion of the substrate,
a first channel region disposed between the first source region and the first drain region, the first channel region having a first type of strain, and
a first gate disposed above the first channel region and between the first source and first drain regions, the first gate comprising a conductive material;
a first trench structure disposed in a trench; and
a first strain-inducing element that induces the first type of strain in the first channel region,
wherein the trench bounds the first source region and the first drain region, the first trench structure and the first strain-inducing element each inducing only a portion of the first type of strain in the first channel region, the first type of strain being selected from the group consisting of tensile and compressive strain.
15. The structure of claim 11 wherein the first type of strain is tensile and the second type of strain is compressive.
16. The structure of claim 11 wherein the first type of strain is compressive and the second type of strain is tensile.
17. The structure of claim 1 , wherein the proximate material comprises an underlying layer.
18. The structure of claim 1 , wherein the proximate material comprises a second material disposed in at least one of the first source and first drain regions.
19. The structure of claim 1 , wherein the trench structure comprises a liner dielectric, a protective liner, and a dielectric material.
20. The structure of claim 3 , wherein the proximate material comprises an underlying layer.
21. The structure of claim 3 , wherein the proximate material comprises a second material disposed in at least one of the first source and first drain regions.
22. The structure of claim 3 , wherein the trench structure comprises a liner dielectric, a protective liner, and a dielectric material.