Three dimensional flash cell
A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.
1. A memory cell, comprising:
a substrate having a pillar of semiconductive material;
two source regions and a drain region formed in the substrate, the source and drain regions substantially vertically separated, and defining a first channel between the first source region and the drain region and a second channel between the second source region and the drain region, the source regions on opposite sides of the substrate pillar;
a first floating gate structure adjacent the first channel, formed in a substantially vertical orientation;
a first control gate structure adjacent the first floating gate, formed in a substantially vertical orientation;
a second floating gate structure adjacent the second channel, formed in a substantially vertical orientation; and
a second control gate structure adjacent the second floating gate, formed in a substantially vertical orientation;
wherein the first and second control gate structures are not contiguous.
2. The memory cell of claim 1 wherein adjacent cells in a row of cells are isolated from each other by an isolation region.
3. The memory cell of claim 2 wherein the source regions run parallel to the isolation regions.
4. The memory cell of claim 1 wherein adjacent rows of cells in an array are staggered from one another so that the cells are arrayed in an offset pattern.
5. The memory cell of claim 1 wherein the substrate is comprised of a p-type silicon.
6. The memory cell of claim 1 and further including an oxide-nitride-oxide layer between each floating gate structure and its respective control gate structure.
7. The memory cell of claim 1 and further including an oxide layer between each floating gate structure and its respective control gate structure.
8. A memory cell, comprising:
a substrate having a pillar of semiconductive material;
two source regions and a drain region formed in the substrate, the drain region substantially vertically separated from each source region, a first channel region defined between the first source region and the drain region and a second channel region defined between the second source region and the drain region, the source regions located on opposite sides of the substrate pillar;
a first insulating layer formed on either side of the pillar;
a floating gate structure formed substantially adjacent to each channel region and in a substantially vertical orientation;
a second insulating layer formed over each floating gate structure; and
a control gate structure formed over each second insulating layer in a substantially vertical orientation wherein adjacent control gates are separated by an isolation area.
9. The memory cell of claim 8 wherein the first and second insulating layers are oxide materials.
10. The memory cell of claim 8 and further including a dielectric layer formed over the memory cell.
11. The memory cell of claim 10 and further including a metal contact formed through the dielectric layer to the drain region such that other drain regions in a memory array are coupled by the metal contact.
12. The memory cell of claim 10 wherein the dielectric layer is comprised of boro-phospho-silicate glass.
13. The memory cell of claim 10 wherein the dielectric layer is comprised of phospho-silicate glass.