Vertical transistors

1. A method of forming an integrated circuit including a vertical transistor comprising:

defining a ridge in a ridge region and a trench adjacent to the ridge in a substrate;

forming a bit line within the trench;

depositing an insulating material in the trench to isolate the bit line;

forming a transistor pillar over the ridge region after depositing the insulating material in the trench, wherein the ridge is adjacent to the trench and extends from a bottom level of the trench to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, wherein the transistor pillar extends upwardly from the shoulder of the ridge, wherein the trench extends from the bottom level to the shoulder, and wherein the bit line is below the shoulder within the trench;

exposing a portion of the bit line adjacent to the ridge region after forming the transistor pillar;

creating a bit line stitch within the trench connecting the bit line to a lower active area within the ridge region after exposing the portion of the bit line, providing the lower active area to comprise one source/drain region of the vertical transistor;

forming a gate surrounding the transistor pillar after creating the bit line stitch; and

providing a lower portion of the pillar to comprise a channel region of the vertical transistor and providing an upper region of the pillar to comprise another source/drain region of the vertical transistor.

2. The method of claim 1 , further comprising forming a gate dielectric surrounding the transistor pillar.

3. The method of claim 1 , wherein creating the bit line stitch comprises depositing polysilicon.

4. The method of claim 3 , wherein depositing polysilicon comprises depositing polysilicon with dopants.

5. The method of claim 4 , wherein creating the bit line stitch comprises outdiffusing the dopants to form the lower active area.

6. The method of claim 1 , wherein forming the transistor pillar comprises forming an epitaxial silicon pillar.

7. A method of forming an integrated circuit comprising a plurality of field effect transistors, individual of the field effect transistors comprising a pair of source/drain regions, a gate comprised by a word line, and a channel region, the method comprising:

forming a bit line within each of a plurality of trenches in a substrate;

forming a plurality of transistor pillars on each of a plurality of ridges in the substrate after forming the bit lines, each ridge extending from a bottom level of the trenches to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, each trench extending from the bottom level to the shoulder, each transistor pillar extending upwardly from the shoulder of the ridge, the bit line being buried below the shoulder in each trench, wherein forming the transistor pillars comprises defining a column of transistor pillars on each ridge and rows of transistor pillars across different ridges, wherein the plurality of ridges alternate with and separate the plurality of trenches;

forming a word line to connect each row of transistor pillars;

creating a plurality of exposed bit line windows in the trenches after forming the word lines;

forming a bit line stitch in each exposed bit line window to connect the bit lines to individual lower active areas received beneath individual of the transistor pillars;and

providing individual of the lower active areas to comprise one of the pair of source/drain regions of one of the field effect transistors and providing the individual transistor pillars received over the respective lower active areas to comprise the channel region and the other of the pair of source/drain regions of the same one of the field effect transistors.

8. The method of claim 7 , further comprising forming a capacitor electrically connected to the other of the pair of source/drain regions over each of the transistor pillars.

9. The method of claim 8 , wherein forming the capacitor comprises forming a container capacitor.

10. The method of claim 7 , wherein forming the bit line stitch comprises depositing polysilicon.

11. The method of claim 10 , wherein forming the bit line stitch comprises depositing polysilicon with n-dopants.

12. The method of claim 11 , further comprising outdiffusing the n-dopants in the bit line stitch into the substrate to form the lower active area of each transistor.

13. The method of claim 7 , wherein forming the transistor pillars comprises:

forming a first mask having a plurality of lines over the substrate;

forming a second mask between the lines of the first mask wherein the first mask and the second mask form a plurality of exposed substrate islands;

providing a spacer layer over the first mask and lining the second mask and the exposed substrate islands;

punching a contact through the spacer layer to the exposed substrate islands; and

growing epitaxial silicon within the exposed substrate island after punching the contact.

14. A method of forming an integrated circuit comprising a plurality of field effect transistors, individual of the field effect transistors comprising a pair of source/drain regions, a gate comprised by a word line, and a channel region, the method comprising:

forming a plurality of trenches separating a plurality of plateaus within a substrate;

depositing a bit line in each trench;

isolating the bit line within each trench;

forming an exposed side portion of the bit line;

depositing a bit line strap connecting the exposed side portion of the bit line to a plurality of lower active areas in the plateaus;

etching the plateaus to form transistor pillars and ridges in the substrate, each ridge extending from a bottom level of the trenches to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, each trench extending from the bottom level to the shoulder, each transistor pillar extending upwardly from the shoulder of the ridge, the bit line being buried below the shoulder in each trench;

depositing a word line material surrounding the transistor pillars;

forming vertical self-alignment spacers surrounding an upper portion of the transistor pillars and over the word line material;

etching the word line material to form a plurality of word lines connecting a row of transistor pillars; and

providing individual of the lower active areas to comprise one of the pair of source/drain regions of one of the field effect transistors and providing the individual transistor pillars received over the respective lower active areas to comprise the channel region and the other of the pair of source/drain regions of the same one of the field effect transistors.

15. The method of claim 14 , wherein the substrate comprises bulk silicon.

16. The method of claim 14 , wherein depositing the bit line strap comprises depositing polysilicon.

17. The method of claim 16 , wherein depositing the bit line strap comprises depositing polysilicon with n-dopants.

18. The method of claim 17 , further comprising outdiffusing the n-dopants in the bit line strap into the substrate to form the lower active areas.

19. The method of claim 14 , wherein etching the plateaus to form transistor pillars comprises:

forming a first mask over the substrate, wherein the first mask has a plurality of holes

depositing a second mask within the holes of the first mask;

removing the first mask after depositing the second mask; and

etching the substrate selectively to the second mask to form transistor pillars.

20. The method of claim 14 , further comprising forming a capacitor over and electrically connected to each transistor pillar.

21. The method of claim 20 , wherein forming the capacitor comprises forming a container capacitor.

22. A method of forming vertical transistors for a memory array comprising:

forming a plurality of buried bit lines within a plurality of trenches in a substrate, the plurality of trenches being separated by a plurality of ridges, each ridge extending from a bottom level of the trenches to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, each trench extending from the bottom level to the shoulder, the bit line being buried below the shoulder in each trench,;

depositing a first mask on the substrate over the trenches and the ridges;

forming a plurality of holes in the first mask;

depositing a second mask in the holes of the first mask

removing the first mask after depositing the second mask;

etching the substrate selectively to the second mask to form a plurality of transistor pillars extending above and adjacent to the buried bit lines, each transistor pillar extending upwardly from the shoulder of the ridge; and

providing individual of the transistor pillars to comprise a channel region and one source/drain region of an individual of the vertical transistors, another source/drain region of said individual of the vertical transistors being provided to be received within the ridge beneath said individual of the transistor pillars.

23. The method of claim 22 , wherein forming the plurality of holes in the first mask comprises forming holes in the first mask over the ridges.